q8(Ǵ 0,Toradex Colibri iMX8DX on Colibri Iris V2 Board?2toradex,colibri-imx8x-iris-v2toradex,colibri-imx8xfsl,imx8dxaliases =/bus@5b000000/ethernet@5b040000 G/bus@5b000000/ethernet@5b050000Q/bus@5d000000/gpio@5d080000W/bus@5d000000/gpio@5d090000]/bus@5d000000/gpio@5d0a0000c/bus@5d000000/gpio@5d0b0000i/bus@5d000000/gpio@5d0c0000o/bus@5d000000/gpio@5d0d0000u/bus@5d000000/gpio@5d0e0000{/bus@5d000000/gpio@5d0f0000/bus@5a000000/i2c@5a800000/bus@5a000000/i2c@5a810000/bus@5a000000/i2c@5a820000/bus@5a000000/i2c@5a830000/bus@5b000000/mmc@5b010000/bus@5b000000/mmc@5b020000/bus@5b000000/mmc@5b030000/bus@5d000000/mailbox@5d1b0000/bus@5d000000/mailbox@5d1c0000/bus@5d000000/mailbox@5d1d0000/bus@5d000000/mailbox@5d1e0000/bus@5d000000/mailbox@5d1f0000/bus@5a000000/serial@5a060000/bus@5a000000/serial@5a070000/bus@5a000000/serial@5a080000/bus@5a000000/serial@5a090000 /vpu@2c000000/vpu-core@2d080000 /vpu@2c000000/vpu-core@2d090000"/bus@5a000000/i2c@5a810000/rtc@68/system-controller/rtccpus cpu@0cpu2arm,cortex-a35psci!@3@M@_l } cpu@1cpu2arm,cortex-a35psci!@3@M@_l } l2-cache02cache#@5opp-table2operating-points-v2opp-9000000005B@Iopp-1200000000GIinterrupt-controller@51a00000 2arm,gic-v3 QQ  , reserved-memory 7decoder-boot@84000000>encoder-boot@86000000 >decoder-rpc@92000000>dsp@92400000@> Edisabledencoder-rpc@94400000@p>pmu2arm,cortex-a35-pmu ,psci 2arm,psci-1.0 smcsystem-controller 2fsl,imx-scu Ltx0rx0gip3$Wpower-controller2fsl,imx8qxp-scu-pdfsl,scu-pd^ clock-controller2fsl,imx8qxp-clkfsl,scu-clkrpinctrl2fsl,imx8qxp-iomuxcdefaultxad7879intgrp !Oadc0grp0d`c`h`g`atmeladaptergrpN!M!atmelconnectorgrp!!canintgrp @csictlgrp  csimclkgrp Aextio0grp 1@fec1grpx5 4 &a%a'a(a-a.a/a0ahfec1slpgrpx5A4A&A%A'A(A-A.A/A0Aiflexcan0grpj!i!flexcan1grpl!k!flexcan2grpn!m!gpioblongrp `gpiohpdgrp z gpiokeysgrp pAzhog0grpa S a, a T a U aR a      X   hog1grp  hog2grp  hogscfwgrp  i2c0grp!!Mi2c0mipilvds0grpt u i2c0mipilvds1grpx y i2c1grpv!w!Rlcdifgrp,L`H`K`J@@7``8`9`:`;`<`=`>`?`@`A`B`C`E`F`G`I`)`P`lpspi2grp0Y!Z@[@\@>lpspi2cs2grp *!lpuart0grp0o p i j Clpuart2grpr q Flpuart3grpm n Hlpuart3ctrlgrpH{ V W    Ipciebgrp$aa`pwmagrpa``pwmbgrp M`rpwmcgrp N`tpwmdgrpaO`vsai0grp0^@a@]@_@sgtl5000grp Asgtl5000usbclkgrp e!Nusb3503agrp ausbcdetgrp 3@usbh1reggrp @usdhc1grp A ! ! ! !!!!!!A![usdhc1-100mhzgrp A ! ! ! !!!!!!A!\usdhc1-200mhzgrp A ! ! ! !!!!!!A!]usdhc2gpiogrp !ausdhc2gpioslpgrp `eusdhc2grpTA! !!!"!#!!`usdhc2-100mhzgrpTA! !!!"!#!!busdhc2-200mhzgrpTA! !!!"!#!!cusdhc2slpgrpT`` `!`"`#`!dwifigrp  gpioirisgrpT  R U T , S uart1forceoffgrp  uart23forceoffgrp { enable-3v3-vmmc-grp X {lvds-converter-grp0l k   ocotp2fsl,imx8qxp-scu-ocotp keys"2fsl,imx8qxp-sc-keyfsl,imx-sc-keyt Edisabledrtc2fsl,imx8qxp-sc-rtcwatchdog"2fsl,imx8qxp-sc-wdtfsl,imx-sc-wdt<thermal-sensor*2fsl,imx8qxp-sc-thermalfsl,imx-sc-thermaltimer2arm,armv8-timer0,   clock-dummy 2fixed-clockr clk_dummyclock-xtal32k 2fixed-clockr xtal_32KHzclock-xtal24m 2fixed-clockrn6 xtal_24MHzthermal-zonescpu0-thermal ctripstrip0(_4passive trip1((4 criticalcooling-mapsmap0? D clock-img-ipg 2fixed-clockr  img_ipg_clkbus@58000000 2simple-bus 7XXjpegdec@58400000X@ ,5} S c x  2nxp,imx8qxp-jpgdecEokayjpegenc@58450000XE ,1}Sc x  2nxp,imx8qxp-jpgencEokayclock-controller@585d00002fsl,imx8qxp-lpcgX]r}0img_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clkx  clock-controller@585f00002fsl,imx8qxp-lpcgX_r}0img_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clkx vpu@2c000000 7,,,x  Edisabledmailbox@2d0000002fsl,imx6sx-mu- ,x  Edisabledmailbox@2d0200002fsl,imx6sx-mu- ,x  Edisabledvpu-core@2d080000-2nxp,imx8q-vpu-decoderx  Ltx0tx1rx$W Edisabledvpu-core@2d090000-2nxp,imx8q-vpu-encoderx  Ltx0tx1rx$W Edisabledclock-cm40-ipg 2fixed-clockr) cm40_ipg_clkbus@34000000 2simple-bus 744serial@372200002fsl,imx8qxp-lpuart7",} ipgbaud Scn6x  Edisabledi2c@37230000$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c7#, }peripg S cn6x   Edisabledintmux@374000002fsl,imx-intmux7@`,}ipgx ! Edisabledclock-controller@376200002fsl,imx8qxp-lpcg7br}*cm40_lpcg_uart_clkcm40_lpcg_uart_ipg_clkx clock-controller@376300002fsl,imx8qxp-lpcg7cr} (cm40_lpcg_i2c_clkcm40_lpcg_i2c_ipg_clkx  bus@53000000 2simple-bus 7SSgpu@53100000 2vivante,gcS ,@} coreshaderSc,E,Ex clock-audio-ipg 2fixed-clockr'audio_ipg_clkclock-ext-aud-mclk0 2fixed-clockrext_aud_mclk0-clock-ext-aud-mclk1 2fixed-clockrext_aud_mclk1.clock-esai0-rx 2fixed-clockr esai0_rx_clk/clock-esai0-rx-hf 2fixed-clockresai0_rx_hf_clk0clock-esai0-tx 2fixed-clockr esai0_tx_clk1clock-esai0-tx-hf 2fixed-clockresai0_tx_hf_clk2clock-spdif0-rx 2fixed-clockr spdif0_rx3clock-sai0-rx-bclk 2fixed-clockr sai0_rx_bclk4clock-sai0-tx-bclk 2fixed-clockr sai0_tx_bclk5clock-sai1-rx-bclk 2fixed-clockr sai1_rx_bclk6clock-sai1-tx-bclk 2fixed-clockr sai1_tx_bclk7clock-sai2-rx-bclk 2fixed-clockr sai2_rx_bclk8clock-sai3-rx-bclk 2fixed-clockr sai3_rx_bclk9clock-sai4-rx-bclk 2fixed-clockr sai4_rx_bclk:bus@59000000 2simple-bus 7YYasrc@590000002fsl,imx8qm-asrcY ,td}memipgasrck_0asrck_1asrck_2asrck_3asrck_4asrck_5asrck_6asrck_7asrck_8asrck_9asrck_aasrck_basrck_casrck_dasrck_easrck_fspba`rxarxbrxctxatxbtxc@x  Edisabledesai@590100002fsl,imx8qm-esaiY ,}coreextalfsysspba rxtxx  Edisabledspdif@590200002fsl,imx8qm-spdifY,0}:corerxtx0rxtx1rxtx2rxtx3rxtx4rxtx5rxtx6rxtx7spba  rxtxx  Edisabledsai@590400002fsl,imx8qm-saiY ,:}busmclk0mclk1mclk2mclk3rxtx   x > Edisabledsai@590500002fsl,imx8qm-saiY ,<}  busmclk0mclk1mclk2mclk3rxtx x ? Edisabledsai@590600002fsl,imx8qm-saiY ,>}!!busmclk0mclk1mclk2mclk3rxx @ Edisabledsai@590700002fsl,imx8qm-saiY ,C}""busmclk0mclk1mclk2mclk3rxx  Edisableddma-controller@591f00002fsl,imx8qm-edmaY\  ,vwxyz{;;==?Dx @ A B C D E F G H I J K L M N O P Q R S T U V Wclock-controller@594000002fsl,imx8qxp-lpcgY@r}asrc0_lpcg_ipg_clkx clock-controller@594100002fsl,imx8qxp-lpcgYAr }(esai0_lpcg_extal_clkesai0_lpcg_ipg_clkx clock-controller@594200002fsl,imx8qxp-lpcgYBr }%spdif0_lpcg_tx_clkspdif0_lpcg_gclkwx clock-controller@594400002fsl,imx8qxp-lpcgYDr } !sai0_lpcg_mclksai0_lpcg_ipg_clkx >clock-controller@594500002fsl,imx8qxp-lpcgYEr } !sai1_lpcg_mclksai1_lpcg_ipg_clkx ? clock-controller@594600002fsl,imx8qxp-lpcgYFr }!sai2_lpcg_mclksai2_lpcg_ipg_clkx @!clock-controller@594700002fsl,imx8qxp-lpcgYGr }!sai3_lpcg_mclksai3_lpcg_ipg_clkx "clock-controller@595900002fsl,imx8qxp-lpcgYYr}dsp_ram_lpcg_ipg_clkx asrc@598000002fsl,imx8qm-asrcY ,|d}##memipgasrck_0asrck_1asrck_2asrck_3asrck_4asrck_5asrck_6asrck_7asrck_8asrck_9asrck_aasrck_basrck_casrck_dasrck_easrck_fspba`$$$$$$rxarxbrxctxatxbtxc@x  Edisabledsai@598200002fsl,imx8qm-saiY ,I}%%busmclk0mclk1mclk2mclk3 $$ rxtxx  Edisabled(sai@598300002fsl,imx8qm-saiY ,K}&&busmclk0mclk1mclk2mclk3$ txx  Edisabled)amix@598400002fsl,imx8qm-audmixY}'ipgx () Edisabledmqs@598500002fsl,imx8qm-mqsY}** mclkcorex  Edisableddma-controller@599f00002fsl,imx8qm-edmaY  ,~JJLXx l m n o p q r s t u v$clock-controller@59d000002fsl,imx8qxp-lpcgYr }Eaud_rec_clk0_lpcg_clkx E+clock-controller@59d100002fsl,imx8qxp-lpcgYr }aud_rec_clk1_lpcg_clkx ,clock-controller@59d200002fsl,imx8qxp-lpcgYr }Eaud_pll_div_clk0_lpcg_clkx Eclock-controller@59d300002fsl,imx8qxp-lpcgYr }aud_pll_div_clk1_lpcg_clkx clock-controller@59d500002fsl,imx8qxp-lpcgYr}mclkout0_lpcg_clkx clock-controller@59d600002fsl,imx8qxp-lpcgYr}mclkout1_lpcg_clkx acm@59e000002fsl,imx8qxp-acmYrx     E     > ? @     X}+,-./0123456789:aud_rec_clk0_lpcg_clkaud_rec_clk1_lpcg_clkaud_pll_div_clk0_lpcg_clkaud_pll_div_clk1_lpcg_clkext_aud_mclk0ext_aud_mclk1esai0_rx_clkesai0_rx_hf_clkesai0_tx_clkesai0_tx_hf_clkspdif0_rxsai0_rx_bclksai0_tx_bclksai1_rx_bclksai1_tx_bclksai2_rx_bclksai3_rx_bclksai4_rx_bclkclock-controller@59c000002fsl,imx8qxp-lpcgYr}asrc1_lpcg_ipg_clkx #clock-controller@59c200002fsl,imx8qxp-lpcgYr }!sai4_lpcg_mclksai4_lpcg_ipg_clkx %clock-controller@59c300002fsl,imx8qxp-lpcgYr }!sai5_lpcg_mclksai5_lpcg_ipg_clkx &clock-controller@59c400002fsl,imx8qxp-lpcgYr}amix_lpcg_ipg_clkx 'clock-controller@59c500002fsl,imx8qxp-lpcgYr }!mqs0_lpcg_mclkmqs0_lpcg_ipg_clkx *clock-dma-ipg 2fixed-clockr' dma_ipg_clkKbus@5a000000 2simple-bus 7ZZspi@5a0000002fsl,imx7ulp-spiZ  ,P};;peripg S5cx 5 Edisabledspi@5a0100002fsl,imx7ulp-spiZ  ,Q}<<peripg S6cx 6 Edisabledspi@5a0200002fsl,imx7ulp-spiZ  ,R}==peripg S7cx 7Eokaydefault> ?spi@5a0300002fsl,imx7ulp-spiZ  ,S}@@peripg S8cx 8 Edisabledserial@5a060000Z ,Y}AA ipgbaud S9cĴx 9rxtx BB Eokay2fsl,imx8qxp-lpuartdefaultCserial@5a070000Z ,Z}DD ipgbaud S:cĴx :rxtx B B  Edisabled2fsl,imx8qxp-lpuartserial@5a080000Z ,[}EE ipgbaud S;cĴx ;rxtx B B Eokay2fsl,imx8qxp-lpuartdefaultFserial@5a090000Z  ,\}GG ipgbaud S<cĴx <rxtx BBEokay2fsl,imx8qxp-lpuartdefaultHIpwm@5a1900002fsl,imx8qxp-pwmfsl,imx27-pwmZ ,}JJipgper Scn6%x dma-controller@5a1f00002fsl,imx8qm-edmaZ,x              Bclock-controller@5a4000002fsl,imx8qxp-lpcgZ@r}5K spi0_lpcg_clkspi0_lpcg_ipg_clkx 5;clock-controller@5a4100002fsl,imx8qxp-lpcgZAr}6K spi1_lpcg_clkspi1_lpcg_ipg_clkx 6<clock-controller@5a4200002fsl,imx8qxp-lpcgZBr}7K spi2_lpcg_clkspi2_lpcg_ipg_clkx 7=clock-controller@5a4300002fsl,imx8qxp-lpcgZCr}8K spi3_lpcg_clkspi3_lpcg_ipg_clkx 8@clock-controller@5a4600002fsl,imx8qxp-lpcgZFr}9K'uart0_lpcg_baud_clkuart0_lpcg_ipg_clkx 9Aclock-controller@5a4700002fsl,imx8qxp-lpcgZGr}:K'uart1_lpcg_baud_clkuart1_lpcg_ipg_clkx :Dclock-controller@5a4800002fsl,imx8qxp-lpcgZHr};K'uart2_lpcg_baud_clkuart2_lpcg_ipg_clkx ;Eclock-controller@5a4900002fsl,imx8qxp-lpcgZIr}<K'uart3_lpcg_baud_clkuart3_lpcg_ipg_clkx <Gclock-controller@5a5900002fsl,imx8qxp-lpcgZYr}K(adma_pwm_lpcg_clkadma_pwm_lpcg_ipg_clkx Ji2c@5a800000Z@ ,}LLperipg S`cn6x `Eokay$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c defaultMNtouchscreen@2c 2adi,ad7879-1defaultO,P,0Ix`{ Edisabledi2c@5a810000Z@ ,}QQperipg Sacn6x aEokay$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2c defaultRrtc@68 2st,m41t0hi2c@5a820000Z@ ,}SSperipg Sbcn6x b Edisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2ci2c@5a830000Z@ ,}TTperipg Sccn6x c Edisabled$2fsl,imx8qxp-lpi2cfsl,imx7ulp-lpi2cadc@5a8800002nxp,imx8qxp-adcZ ,}UUperipg Secn6x e Edisabledcan@5a8d00002fsl,imx8qm-flexcanZ ,}VVipgper SicbZx i Edisabledcan@5a8e00002fsl,imx8qm-flexcanZ ,}VVipgper SicbZx j Edisabledcan@5a8f00002fsl,imx8qm-flexcanZ ,}VVipgper SicbZx k Edisableddma-controller@5a9f00002fsl,imx8qm-edmaZ `,@x        clock-controller@5ac000002fsl,imx8qxp-lpcgZr}`K i2c0_lpcg_clki2c0_lpcg_ipg_clkx `Lclock-controller@5ac100002fsl,imx8qxp-lpcgZr}aK i2c1_lpcg_clki2c1_lpcg_ipg_clkx aQclock-controller@5ac200002fsl,imx8qxp-lpcgZr}bK i2c2_lpcg_clki2c2_lpcg_ipg_clkx bSclock-controller@5ac300002fsl,imx8qxp-lpcgZr}cK i2c3_lpcg_clki2c3_lpcg_ipg_clkx cTclock-controller@5ac800002fsl,imx8qxp-lpcgZr}eK adc0_lpcg_clkadc0_lpcg_ipg_clkx eUclock-controller@5acd00002fsl,imx8qxp-lpcgZr}iKK 5can0_lpcg_pe_clkcan0_lpcg_ipg_clkcan0_lpcg_chi_clkx iVclock-conn-axi 2fixed-clockrCU conn_axi_clkoclock-conn-ahb 2fixed-clockr ! conn_ahb_clkpclock-conn-ipg 2fixed-clockr conn_ipg_clknbus@5b000000 2simple-bus 7[[usb@5b0d0000-2fsl,imx7ulp-usbfsl,imx6ul-usbfsl,imx27-usb[  , WX}Y$8x  Edisabledusbmisc@5b0d0200L82fsl,imx7ulp-usbmiscfsl,imx7d-usbmiscfsl,imx6q-usbmisc[ Xusbphy@5b1000002fsl,imx7ulp-usbphy[}Yx  EdisabledWmmc@5b010000 ,[}ZZZ ipgahbperx Eokay"2fsl,imx8qxp-usdhcfsl,imx7d-usdhcYcqw"defaultstate_100mhzstate_200mhz[\]mmc@5b020000 ,[}^^^ ipgahbperx Eokay"2fsl,imx8qxp-usdhcfsl,imx7d-usdhcY P _(defaultstate_100mhzstate_200mhzsleep`abacademmc@5b030000 ,[}fff ipgahbperx  Edisabled"2fsl,imx8qxp-usdhcfsl,imx7d-usdhcethernet@5b040000[0, }ggg gipgahbenet_clk_refptpSc沀sY@x Eokay.2fsl,imx8qxp-fecfsl,imx8qm-fecfsl,imx6sx-fecdefaultsleephirmii"j-mdio ethernet-phy@22ethernet-phy-ieee802.3-c22>djethernet@5b050000[0, }kkk kipgahbenet_clk_refptpSc沀sY@x  Edisabled.2fsl,imx8qxp-fecfsl,imx8qm-fecfsl,imx6sx-fecusb@5b1100002fsl,imx8qm-usb3[ 7(}llllllpmbusaclkipgcore Sc沀x  Edisabledusb@5b120000 2cdns,usb3[[[ Hotgxhcidev0,Rhostperipheralotgwakeupbmgcdns3,usb3-phyq Edisabledusb-phy@5b1600002nxp,salvo-phy[}lsalvo_phy_clkx  Edisabledmclock-controller@5b2000002fsl,imx8qxp-lpcg[ r}no 9sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clkx Zclock-controller@5b2100002fsl,imx8qxp-lpcg[!r}no 9sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clkx ^clock-controller@5b2200002fsl,imx8qxp-lpcg["r}no 9sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clkx fclock-controller@5b2300002fsl,imx8qxp-lpcg[#r0}onn enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clkx gclock-controller@5b2400002fsl,imx8qxp-lpcg[$r0}onn enet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clkx kclock-controller@5b2700002fsl,imx8qxp-lpcg['r}pn"usboh3_ahb_clkusboh3_phy_ipg_clkx Yclock-controller@5b2800002fsl,imx8qxp-lpcg[(r0}nnnMusb3_app_clkusb3_lpm_clkusb3_ipg_clkusb3_core_pclkusb3_phy_clkusb3_aclkx lbus@5c000000 2simple-bus 7\\ddr-pmu@5c0200002fsl,imx8-ddr-pmu\ ,clock-lsio-bus 2fixed-clockr lsio_bus_clkybus@5d000000 2simple-bus  7]]pwm@5d0000002fsl,imx27-pwm]ipgper}qq Scn6% ,^Eokayrdefaultpwm@5d0100002fsl,imx27-pwm]ipgper}ss Scn6% ,_Eokaytdefaultpwm@5d0200002fsl,imx27-pwm]ipgper}uu Scn6% ,`Eokayvdefaultpwm@5d0300002fsl,imx27-pwm]ipgper}ww Scn6% ,a Edisabledgpio@5d080000] ,x  2fsl,imx8qxp-gpiofsl,imx35-gpioPx8 x ExKxPxRSODIMM_70SODIMM_60SODIMM_58SODIMM_78SODIMM_72SODIMM_80SODIMM_46SODIMM_62SODIMM_48SODIMM_74SODIMM_50SODIMM_52SODIMM_54SODIMM_66SODIMM_64SODIMM_68SODIMM_82SODIMM_56SODIMM_28SODIMM_30SODIMM_61SODIMM_103SODIMM_25SODIMM_27SODIMM_100|gpio@5d090000]  ,x  2fsl,imx8qxp-gpiofsl,imx35-gpio0xY x cxt SODIMM_86SODIMM_92SODIMM_90SODIMM_88SODIMM_59SODIMM_6SODIMM_8SODIMM_2SODIMM_4SODIMM_34SODIMM_32SODIMM_63SODIMM_55SODIMM_33SODIMM_35SODIMM_36SODIMM_38SODIMM_21SODIMM_19SODIMM_140SODIMM_142SODIMM_196SODIMM_194SODIMM_186SODIMM_188SODIMM_138?gpio@5d0a0000]  ,x  2fsl,imx8qxp-gpiofsl,imx35-gpio0x{x~xSODIMM_23SODIMM_144gpio@5d0b0000]  ,x  2fsl,imx8qxp-gpiofsl,imx35-gpio0xx xSODIMM_96SODIMM_75SODIMM_37SODIMM_29SODIMM_43SODIMM_45SODIMM_69SODIMM_71SODIMM_73SODIMM_77SODIMM_89SODIMM_93SODIMM_95SODIMM_99SODIMM_105SODIMM_107SODIMM_98SODIMM_102SODIMM_104SODIMM_106Plvds-tx-on-hoggpio@5d0c0000]  ,x  2fsl,imx8qxp-gpiofsl,imx35-gpioxxx x xxxx%SODIMM_129SODIMM_133SODIMM_127SODIMM_131SODIMM_44SODIMM_76SODIMM_31SODIMM_47SODIMM_190SODIMM_192SODIMM_49SODIMM_51SODIMM_53gpio@5d0d0000]  ,x  2fsl,imx8qxp-gpiofsl,imx35-gpio0x(x,x 3aSODIMM_57SODIMM_65SODIMM_85SODIMM_135SODIMM_137UNUSABLE_SODIMM_180UNUSABLE_SODIMM_184gpio@5d0e0000] ,x  2fsl,imx8qxp-gpiofsl,imx35-gpiogpio@5d0f0000] ,x  2fsl,imx8qxp-gpiofsl,imx35-gpiospi@5d120000 2nxp,imx8qxp-fspi]Hfspi_basefspi_mmap ,\} fspi_enfspix  Edisabledmailbox@5d1b0000] , Edisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1c0000] ,-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1d0000] , Edisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1e0000] , Edisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d1f0000] , Edisabled-2fsl,imx8-mu-scufsl,imx8qxp-mufsl,imx6sx-mumailbox@5d200000]  ,x  Edisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d210000]! ,x  Edisabled2fsl,imx8qxp-mufsl,imx6sx-mumailbox@5d280000]( ,x 2fsl,imx8qxp-mufsl,imx6sx-muclock-controller@5d4000002fsl,imx8qxp-lpcg]@r4}yhpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clkx qclock-controller@5d4100002fsl,imx8qxp-lpcg]Ar4}yhpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clkx sclock-controller@5d4200002fsl,imx8qxp-lpcg]Br4}yhpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clkx uclock-controller@5d4300002fsl,imx8qxp-lpcg]Cr4}yhpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clkx wclock-controller@5d4400002fsl,imx8qxp-lpcg]Dr4}yhpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clkx clock-controller@5d4500002fsl,imx8qxp-lpcg]Er4}yhpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clkx clock-controller@5d4600002fsl,imx8qxp-lpcg]Fr4}yhpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clkx clock-controller@5d4700002fsl,imx8qxp-lpcg]Gr4}yhpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clkx chosen/bus@5a000000/serial@5a090000gpio-keys 2gpio-keysdefaultzEokaykey-wakeup  P Wake-Upregulator-module-3v32regulator-fixed+V3.3,2ZD2Zregulator-3v32regulator-fixedD2Z,2Z3.3Vregulator-3v3-vmmc2regulator-fixeddefault{\ o|D2Z,2Z 3v3_vmmctd_ interrupt-parent#address-cells#size-cellsmodelcompatibleethernet0ethernet1gpio0gpio1gpio2gpio3gpio4gpio5gpio6gpio7i2c0i2c1i2c2i2c3mmc0mmc1mmc2mu0mu1mu2mu3mu4serial0serial1serial2serial3vpu-core0vpu-core1rtc0rtc1device_typeregenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheclocksoperating-points-v2#cooling-cellsphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterruptsrangesno-mapstatusmbox-namesmboxes#power-domain-cells#clock-cellspinctrl-namespinctrl-0fsl,pinslinux,keycodestimeout-sec#thermal-sensor-cellsclock-frequencyclock-output-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-deviceassigned-clocksassigned-clock-ratespower-domainsslotclock-indices#mbox-cellsclock-namesdmasdma-namesfsl,asrc-ratefsl,asrc-widthfsl,asrc-clk-map#dma-cellsdma-channelsdma-channel-maskdaiscs-gpios#pwm-cellstouchscreen-max-pressureadi,resistance-plate-xadi,first-conversion-delayadi,acquisition-timeadi,median-filter-sizeadi,averagingadi,conversion-interval#io-channel-cellsfsl,clk-sourcefsl,scu-indexfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dword#index-cellsbus-widthnon-removableno-sdno-sdiopinctrl-1pinctrl-2fsl,tuning-start-tapfsl,tuning-stepcd-gpiosvmmc-supplypinctrl-3disable-wpcap-power-off-cardfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetmax-speedreg-namesinterrupt-namesphysphy-namescdns,on-chip-buff-size#phy-cellsgpio-controller#gpio-cellsgpio-rangesgpio-line-namesgpio-hogoutput-highstdout-pathdebounce-intervallabellinux,codewakeup-sourceregulator-nameregulator-min-microvoltregulator-max-microvoltenable-active-highgpiostartup-delay-us