@88( ,Freescale i.MX8QM MEK2fsl,imx8qm-mekfsl,imx8qmaliases=/bus@5b000000/mmc@5b010000B/bus@5b000000/mmc@5b020000G/bus@5b000000/mmc@5b030000L/bus@5a000000/serial@5a060000T/bus@5a000000/serial@5a070000\/bus@5a000000/serial@5a080000d/bus@5a000000/serial@5a090000 l/vpu@2c000000/vpu-core@2d080000 v/vpu@2c000000/vpu-core@2d090000 /vpu@2c000000/vpu-core@2d0a0000cpus cpu@0cpu2arm,cortex-a53 psci@@,;cpu@1cpu2arm,cortex-a53 psci@@,; cpu@2cpu2arm,cortex-a53 psci@@,; cpu@3cpu2arm,cortex-a53 psci@@,; l2-cache02cacheCO@;l2-cache12cacheCO@opp-table-02operating-points-v2];opp-600000000h#Fo }Iopp-896000000h5goB@}Iopp-1104000000hAʹo}Iopp-1200000000hGo}Iopp-table-12operating-points-v2]opp-600000000h#FoB@}Iopp-1056000000h>HoB@}Iopp-1296000000hM?do}Iopp-1596000000h_!o}Iinterrupt-controller@51a00000 2arm,gic-v3PQQ R RR  ;pmu2arm,armv8-pmuv3 psci 2arm,psci-1.0smctimer2arm,armv8-timer0   iommu@51400000 2arm,mmu-500Q@                                 ;7system-controller 2fsl,imx-scu tx0rx0gip3$power-controller2fsl,imx8qm-scu-pdfsl,scu-pd; clock-controller2fsl,imx8qm-clkfsl,scu-clk;pinctrl2fsl,imx8qm-iomuxc;Ki2c1grpLL;&i2c1gpio-grpLL;'adc0grp `;,fec1grp              ;?lpspi2grp$z@{@|@;lpspi2csgrp }!;flexspi0grp!!!!!!!!!!!!!!!!;Llpuart0grp  ;lpuart2grp  ;lpuart3grp   ;!usdhc1grpA!!!!!!!!!A;8usdhc2grpTA!!!!!!;:rtc2fsl,imx8qxp-sc-rtcthermal-sensor*2fsl,imx8qxp-sc-thermalfsl,imx-sc-thermal';thermal-zonescpu0-thermal=Satripstrip0q}passive;trip1q} criticalcooling-mapsmap00 gpu0-thermal=Satripstrip0q}passivetrip1q} criticalgpu1-thermal=Satripstrip0q}passivetrip1q} criticaldrc0-thermal=Sa tripstrip0q}passivetrip1q} criticalvpu@2c000000 ,,,  disabledmailbox@2d0000002fsl,imx6sx-mu-   disabled; mailbox@2d0200002fsl,imx6sx-mu-   disabled;mailbox@2d0400002fsl,imx6sx-mu-   disabled;vpu-core@2d080000-2nxp,imx8q-vpu-decoder  tx0tx1rx$   disabledvpu-core@2d090000- 2nxp,imx8q-vpu-encoder  tx0tx1rx$ disabledvpu-core@2d0a0000- 2nxp,imx8q-vpu-encoder  tx0tx1rx$ disabledclock-img-ipg 2fixed-clock  img_ipg_clk;bus@58000000 2simple-bus XXjpegdec@58400000X@ 5    %2nxp,imx8qm-jpgdecnxp,imx8qxp-jpgdecjpegenc@58450000XE 1    %2nxp,imx8qm-jpgencnxp,imx8qxp-jpgencclock-controller@585d00002fsl,imx8qxp-lpcgX]0img_jpeg_dec_lpcg_clkimg_jpeg_dec_lpcg_ipg_clk ;clock-controller@585f00002fsl,imx8qxp-lpcgX_0img_jpeg_enc_lpcg_clkimg_jpeg_enc_lpcg_ipg_clk ;clock-dma-ipg 2fixed-clock' dma_ipg_clk;#bus@5a000000 2simple-bus ZZspi@5a0000002fsl,imx7ulp-spiZ  Pperipg 5 5 disabledspi@5a0100002fsl,imx7ulp-spiZ  Qperipg 6 6 disabledspi@5a0200002fsl,imx7ulp-spiZ  Rperipg 7 7okay+default9 C spi@02rohm,dh2228fvLÀspi@5a0300002fsl,imx7ulp-spiZ  Speripg 8 8 disabledserial@5a060000Z Y ipgbaud 9Ĵ 9^rxtx h  okay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuart+default9serial@5a070000Z Z ipgbaud :Ĵ :^rxtx h disabled%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuartserial@5a080000Z [ ipgbaud ;Ĵ ;^rxtx hokay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuart+default9serial@5a090000Z  \   ipgbaud <Ĵ <^rxtx hokay%2fsl,imx8qm-lpuartfsl,imx8qxp-lpuart+default9!pwm@5a1900002fsl,imx8qxp-pwmfsl,imx27-pwmZ ""ipgper n6m dma-controller@5a1f00002fsl,imx8qm-edmaZx @ A B C D E F G H I J K L M N O P Q R S T Uokay;clock-controller@5a4000002fsl,imx8qxp-lpcgZ@5# spi0_lpcg_clkspi0_lpcg_ipg_clk 5;clock-controller@5a4100002fsl,imx8qxp-lpcgZA6# spi1_lpcg_clkspi1_lpcg_ipg_clk 6;clock-controller@5a4200002fsl,imx8qxp-lpcgZB7# spi2_lpcg_clkspi2_lpcg_ipg_clk 7;clock-controller@5a4300002fsl,imx8qxp-lpcgZC8# spi3_lpcg_clkspi3_lpcg_ipg_clk 8;clock-controller@5a4600002fsl,imx8qxp-lpcgZF9#'uart0_lpcg_baud_clkuart0_lpcg_ipg_clk 9;clock-controller@5a4700002fsl,imx8qxp-lpcgZG:#'uart1_lpcg_baud_clkuart1_lpcg_ipg_clk :;clock-controller@5a4800002fsl,imx8qxp-lpcgZH;#'uart2_lpcg_baud_clkuart2_lpcg_ipg_clk ;;clock-controller@5a4900002fsl,imx8qxp-lpcgZI<#'uart3_lpcg_baud_clkuart3_lpcg_ipg_clk <; clock-controller@5a5900002fsl,imx8qxp-lpcgZY#(adma_pwm_lpcg_clkadma_pwm_lpcg_ipg_clk ;"i2c@5a800000Z@ $$peripg `n6 ` disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a810000Z@ %%peripg an6 aokay#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2c  +defaultgpio9&' ( (i2c@5a820000Z@ ))peripg bn6 b disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2ci2c@5a830000Z@ **peripg cn6 c disabled#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2cadc@5a8800002nxp,imx8qxp-adcZ ++peripg en6 eokay+default9,-adc@5a8900002nxp,imx8qxp-adcZ ..peripg fn6 f disabledcan@5a8d00002fsl,imx8qm-flexcanZ //ipgper ibZ i disabledcan@5a8e00002fsl,imx8qm-flexcanZ 00ipgper jbZ j disabledcan@5a8f00002fsl,imx8qm-flexcanZ 11ipgper kbZ k disableddma-controller@5a9f00002fsl,imx8qm-edmaZ!x xP l m n o p q r s t uclock-controller@5ac000002fsl,imx8qxp-lpcgZ`# i2c0_lpcg_clki2c0_lpcg_ipg_clk `;$clock-controller@5ac100002fsl,imx8qxp-lpcgZa# i2c1_lpcg_clki2c1_lpcg_ipg_clk a;%clock-controller@5ac200002fsl,imx8qxp-lpcgZb# i2c2_lpcg_clki2c2_lpcg_ipg_clk b;)clock-controller@5ac300002fsl,imx8qxp-lpcgZc# i2c3_lpcg_clki2c3_lpcg_ipg_clk c;*clock-controller@5ac800002fsl,imx8qxp-lpcgZe# adc0_lpcg_clkadc0_lpcg_ipg_clk e;+clock-controller@5ac900002fsl,imx8qxp-lpcgZf# adc1_lpcg_clkadc1_lpcg_ipg_clk f;.clock-controller@5acd00002fsl,imx8qxp-lpcgZi## 5can0_lpcg_pe_clkcan0_lpcg_ipg_clkcan0_lpcg_chi_clk i;/clock-controller@5a4a00002fsl,imx8qxp-lpcgZJ=#'uart4_lpcg_baud_clkuart4_lpcg_ipg_clk =i2c@5a840000#2fsl,imx8qm-lpi2cfsl,imx7ulp-lpi2cZ@ X22peripg dn6 d disabledclock-controller@5ac400002fsl,imx8qxp-lpcgZd# i2c4_lpcg_clki2c4_lpcg_ipg_clk d;2clock-controller@5ace00002fsl,imx8qxp-lpcgZj## 5can1_lpcg_pe_clkcan1_lpcg_ipg_clkcan1_lpcg_chi_clk j;0clock-controller@5acf00002fsl,imx8qxp-lpcgZk## 5can2_lpcg_pe_clkcan2_lpcg_ipg_clkcan2_lpcg_chi_clk k;1clock-conn-axi 2fixed-clockCU conn_axi_clk;Eclock-conn-ahb 2fixed-clock ! conn_ahb_clk;Fclock-conn-ipg 2fixed-clock conn_ipg_clk;Dbus@5b000000 2simple-bus [[usb@5b0d0000-2fsl,imx7ulp-usbfsl,imx6ul-usbfsl,imx27-usb[   345"6  disabledusbmisc@5b0d0200J82fsl,imx7ulp-usbmiscfsl,imx7d-usbmiscfsl,imx6q-usbmisc[ ;4usbphy@5b1000002fsl,imx7ulp-usbphy[5  disabled;3mmc@5b010000 [666 ipgahbper okay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhc W7+default98^hnvmmc@5b020000 [999 ipgahbper okay32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhc W7+default9:^; < <mmc@5b030000 [=== ipgahbper  disabled32fsl,imx8qm-usdhcfsl,imx8qxp-usdhcfsl,imx7d-usdhc W7ethernet@5b040000[0 >>> >ipgahbenet_clk_refptp沀sY@ okay2fsl,imx8qm-fecfsl,imx6sx-fec W7+default9? rgmii-id@mdio ethernet-phy@02ethernet-phy-ieee802.3-c22;@ethernet-phy@12ethernet-phy-ieee802.3-c22ethernet@5b050000[0 AAA Aipgahbenet_clk_refptp沀sY@  disabled2fsl,imx8qm-fecfsl,imx6sx-fec W7usb@5b1100002fsl,imx8qm-usb3[ (BBBBBlpmbusaclkipgcore 沀  disabledusb@5b120000 2cdns,usb3[[[ otgxhcidev0hostperipheralotgwakeup*C/cdns3,usb3-phy9 disabledusb-phy@5b1600002nxp,salvo-phy[Bsalvo_phy_clk P disabled;Cclock-controller@5b2000002fsl,imx8qxp-lpcg[ DE 9sdhc0_lpcg_per_clksdhc0_lpcg_ipg_clksdhc0_lpcg_ahb_clk ;6clock-controller@5b2100002fsl,imx8qxp-lpcg[!DE 9sdhc1_lpcg_per_clksdhc1_lpcg_ipg_clksdhc1_lpcg_ahb_clk ;9clock-controller@5b2200002fsl,imx8qxp-lpcg["DE 9sdhc2_lpcg_per_clksdhc2_lpcg_ipg_clksdhc2_lpcg_ahb_clk ;=clock-controller@5b2300002fsl,imx8qxp-lpcg[#0EDD enet0_lpcg_timer_clkenet0_lpcg_txc_sampling_clkenet0_lpcg_ahb_clkenet0_lpcg_rgmii_txc_clkenet0_lpcg_ipg_clkenet0_lpcg_ipg_s_clk ;>clock-controller@5b2400002fsl,imx8qxp-lpcg[$0EDD enet1_lpcg_timer_clkenet1_lpcg_txc_sampling_clkenet1_lpcg_ahb_clkenet1_lpcg_rgmii_txc_clkenet1_lpcg_ipg_clkenet1_lpcg_ipg_s_clk ;Aclock-controller@5b2700002fsl,imx8qxp-lpcg['FD"usboh3_ahb_clkusboh3_phy_ipg_clk ;5clock-controller@5b2800002fsl,imx8qxp-lpcg[(0DDDMusb3_app_clkusb3_lpm_clkusb3_ipg_clkusb3_core_pclkusb3_phy_clkusb3_aclk ;Bclock-lsio-bus 2fixed-clock lsio_bus_clk;Mbus@5d000000 2simple-bus  ]]pwm@5d0000002fsl,imx27-pwm]ipgperGG n6m ^ disabledpwm@5d0100002fsl,imx27-pwm]ipgperHH n6m _ disabledpwm@5d0200002fsl,imx27-pwm]ipgperII n6m ` disabledpwm@5d0300002fsl,imx27-pwm]ipgperJJ n6m a disabledgpio@5d080000] [k 2fsl,imx8qm-gpiofsl,imx35-gpio0wKKK$;(gpio@5d090000]  [k 2fsl,imx8qm-gpiofsl,imx35-gpio@wK(K2 K?KHgpio@5d0a0000]  [k 2fsl,imx8qm-gpiofsl,imx35-gpio0wKPKUKh gpio@5d0b0000]  [k 2fsl,imx8qm-gpiofsl,imx35-gpiowKrKuKKKKKKKKKK;gpio@5d0c0000]  [k 2fsl,imx8qm-gpiofsl,imx35-gpio`wKKKK KK;Ngpio@5d0d0000]  [k 2fsl,imx8qm-gpiofsl,imx35-gpiowKKK KKKKK;<gpio@5d0e0000] [k 2fsl,imx8qm-gpiofsl,imx35-gpio wK K  gpio@5d0f0000] [k 2fsl,imx8qm-gpiofsl,imx35-gpiospi@5d120000 2nxp,imx8qxp-fspi]fspi_basefspi_mmap \ fspi_enfspi okay+default9Lflash@0 2jedec,spi-norLk@mailbox@5d1b0000]  disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1c0000] ,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mu;mailbox@5d1d0000]  disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1e0000]  disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d1f0000]  disabled,2fsl,imx8-mu-scufsl,imx8qm-mufsl,imx6sx-mumailbox@5d200000]    disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d210000]!   disabled2fsl,imx8qm-mufsl,imx6sx-mumailbox@5d280000](  2fsl,imx8qm-mufsl,imx6sx-muclock-controller@5d4000002fsl,imx8qxp-lpcg]@4Mhpwm0_lpcg_ipg_clkpwm0_lpcg_ipg_hf_clkpwm0_lpcg_ipg_s_clkpwm0_lpcg_ipg_slv_clkpwm0_lpcg_ipg_mstr_clk ;Gclock-controller@5d4100002fsl,imx8qxp-lpcg]A4Mhpwm1_lpcg_ipg_clkpwm1_lpcg_ipg_hf_clkpwm1_lpcg_ipg_s_clkpwm1_lpcg_ipg_slv_clkpwm1_lpcg_ipg_mstr_clk ;Hclock-controller@5d4200002fsl,imx8qxp-lpcg]B4Mhpwm2_lpcg_ipg_clkpwm2_lpcg_ipg_hf_clkpwm2_lpcg_ipg_s_clkpwm2_lpcg_ipg_slv_clkpwm2_lpcg_ipg_mstr_clk ;Iclock-controller@5d4300002fsl,imx8qxp-lpcg]C4Mhpwm3_lpcg_ipg_clkpwm3_lpcg_ipg_hf_clkpwm3_lpcg_ipg_s_clkpwm3_lpcg_ipg_slv_clkpwm3_lpcg_ipg_mstr_clk ;Jclock-controller@5d4400002fsl,imx8qxp-lpcg]D4Mhpwm4_lpcg_ipg_clkpwm4_lpcg_ipg_hf_clkpwm4_lpcg_ipg_s_clkpwm4_lpcg_ipg_slv_clkpwm4_lpcg_ipg_mstr_clk clock-controller@5d4500002fsl,imx8qxp-lpcg]E4Mhpwm5_lpcg_ipg_clkpwm5_lpcg_ipg_hf_clkpwm5_lpcg_ipg_s_clkpwm5_lpcg_ipg_slv_clkpwm5_lpcg_ipg_mstr_clk clock-controller@5d4600002fsl,imx8qxp-lpcg]F4Mhpwm6_lpcg_ipg_clkpwm6_lpcg_ipg_hf_clkpwm6_lpcg_ipg_s_clkpwm6_lpcg_ipg_slv_clkpwm6_lpcg_ipg_mstr_clk clock-controller@5d4700002fsl,imx8qxp-lpcg]G4Mhpwm7_lpcg_ipg_clkpwm7_lpcg_ipg_hf_clkpwm7_lpcg_ipg_s_clkpwm7_lpcg_ipg_slv_clkpwm7_lpcg_ipg_mstr_clk chosen/bus@5a000000/serial@5a060000memory@80000000memory@usdhc2-vmmc2regulator-fixed SD1_SPWR-- N;;regulator-adc-vref2regulator-fixed vref_1v8w@w@;- interrupt-parent#address-cells#size-cellsmodelcompatiblemmc0mmc1mmc2serial0serial1serial2serial3vpu-core0vpu-core1vpu-core2device_typeregclocksenable-methodi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2#cooling-cellsphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspend#interrupt-cellsinterrupt-controllerinterrupts#global-interrupts#iommu-cellsmbox-namesmboxes#power-domain-cells#clock-cellsfsl,pins#thermal-sensor-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerangespower-domainsstatus#mbox-cellsclock-frequencyclock-output-namesassigned-clocksassigned-clock-ratesslotclock-indicesclock-namespinctrl-namespinctrl-0cs-gpiosspi-max-frequencydma-namesdmas#pwm-cells#dma-cellsdma-channelsdma-channel-maskpinctrl-1scl-gpiossda-gpios#io-channel-cellsvref-supplyfsl,clk-sourcefsl,scu-indexfsl,usbphyfsl,usbmiscahb-burst-configtx-burst-size-dwordrx-burst-size-dword#index-cellsiommusbus-widthno-sdno-sdionon-removablefsl,tuning-start-tapfsl,tuning-stepvmmc-supplycd-gpioswp-gpiosfsl,num-tx-queuesfsl,num-rx-queuesphy-modephy-handlefsl,magic-packetreg-namesinterrupt-namesphysphy-namescdns,on-chip-buff-size#phy-cellsgpio-controller#gpio-cellsgpio-rangesspi-tx-bus-widthspi-rx-bus-widthstdout-pathregulator-nameregulator-min-microvoltregulator-max-microvoltgpioenable-active-high