8,( 'friendlyarm,nanopi-r4srockchip,rk3399 +7FriendlyElec NanoPi R4Saliases=/pinctrl/gpio@ff720000C/pinctrl/gpio@ff730000I/pinctrl/gpio@ff780000O/pinctrl/gpio@ff788000U/pinctrl/gpio@ff790000[/i2c@ff3c0000`/i2c@ff110000e/i2c@ff120000j/i2c@ff130000o/i2c@ff3d0000t/i2c@ff140000y/i2c@ff150000~/i2c@ff160000/i2c@ff3e0000/serial@ff180000/serial@ff190000/serial@ff1a0000/serial@ff1b0000/serial@ff370000/spi@ff1c0000/spi@ff1d0000/spi@ff1e0000/spi@ff350000/spi@ff1f0000/spi@ff200000/ethernet@fe300000/mmc@fe310000/mmc@fe320000/mmc@fe330000cpus+cpu-mapcluster0core0core1core2core3cluster1core0core1cpu@0cpuarm,cortex-a53psci #2dL \i@{@   cpu@1cpuarm,cortex-a53psci #2dL \i@{@   cpu@2cpuarm,cortex-a53psci #2dL \i@{@   cpu@3cpuarm,cortex-a53psci #2dL \i@{@   cpu@100cpuarm,cortex-a72psci  #2L \i@{@thermal-idle#'cpu@101cpuarm,cortex-a72psci  #2L \i@{@thermal-idle#'l2-cache-cluster0cache^k@} l2-cache-cluster1cache^k@}idle-states"pscicpu-sleeparm,idle-state/@Wxh cluster-sleeparm,idle-state/@Wh memory-controllerrockchip,rk3399-dmcydmc_clk disabledpmu_a53arm,cortex-a53-pmupmu_a72arm,cortex-a72-pmupsci arm,psci-1.0smctimerarm,armv8-timer@   xin24m fixed-clockn6xin24mpcie@f8000000rockchip,rk3399-pcie axi-baseapb-basepci+! Gaclkaclk-perfhclkpm0123+syslegacyclient;`N\k s,xpcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-388(coremgmtmgmt-stickypipepmpclkaclkokayinterrupt-controllerpcie-ep@f8000000rockchip,rk3399-pcie-ep apb-basemem-base Gaclkaclk-perfhclkpm8(coremgmtmgmt-stickypipepmpclkaclk s,xpcie-phy-0pcie-phy-1pcie-phy-2pcie-phy-3 default% disabledethernet@fe300000rockchip,rk3399-gmac0 +macirq8ighfjfMstmmacethmac_clk_rxmac_clk_txclk_mac_refclk_mac_refoutaclk_macpclk_mac/ stmmaceth=JokayUl|inputdefault % !"rgmii#(mdiosnps,dwmac-mdio+ethernet-phy@1 $ 'u0 $"mmc@fe3100000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc1@@р Mbiuciuciu-driveciu-sample/yreset disabled )?%Jdefault %&'(Xmmc@fe3200000rockchip,rk3399-dw-mshcrockchip,rk3288-dw-mshc2@Aрlf  Lbiuciuciu-driveciu-sample/zresetokay { )default%*+,-X./mmc@fe330000+rockchip,rk3399-sdhci-5.1arasan,sdhci-5.13 lNf Nclk_xinclk_ahbemmc_cardclocks0 xphy_arasan/ disabledJusb@fe380000 generic-ehci81s2xusbokayusb@fe3a0000 generic-ohci:1s2xusbokayusb@fe3c0000 generic-ehci<3s4xusbokayusb@fe3e0000 generic-ohci> 3s4xusbokaydebug@fe430000&arm,coresight-cpu-debugarm,primecellCM apb_pclkdebug@fe432000&arm,coresight-cpu-debugarm,primecellC M apb_pclkdebug@fe434000&arm,coresight-cpu-debugarm,primecellC@M apb_pclkdebug@fe436000&arm,coresight-cpu-debugarm,primecellC`M apb_pclkdebug@fe610000&arm,coresight-cpu-debugarm,primecellaL apb_pclkdebug@fe710000&arm,coresight-cpu-debugarm,primecellqL apb_pclkusb@fe800000rockchip,rk3399-dwc3+0Gref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk% usb3-otgokayusb@fe800000 snps,dwc3irefbus_earlysuspendhosts56xusb2-phyusb3-phy utmi_wide:St/okayusb@fe900000rockchip,rk3399-dwc3+0Gref_clksuspend_clkbus_clkaclk_usb3_rksoc_axi_perfaclk_usb3grf_clk& usb3-otgokayusb@fe900000 snps,dwc3nrefbus_earlysuspendhosts78xusb2-phyusb3-phy utmi_wide:St/okaydp@fec00000rockchip,rk3399-cdn-dp lrf  ruocore-clkpclkspdifgrfs9:/ HJspdifdptxapbcore= disabledportsport+endpoint@0;endpoint@1<interrupt-controller@fee00000 arm,gic-v3+P  msi-controller@fee20000arm,gic-v3-itsppi-partitionsinterrupt-partition-0interrupt-partition-1saradc@ff100000rockchip,rk3399-saradc>Pesaradcapb_pclk saradc-apbokaycrypto@ff8b0000rockchip,rk3399-crypto@hclk_masterhclk_slavesclkmasterslavecrypto-rstcrypto@ff8b8000rockchip,rk3399-crypto@hclk_masterhclk_slavesclkmasterslavecrypto-rsti2c@ff110000rockchip,rk3399-i2clAf AU i2cpclk;default%=+okay @i2c@ff120000rockchip,rk3399-i2clBf BV i2cpclk#default%>+okayi2c@ff130000rockchip,rk3399-i2clCf CW i2cpclk"default%?+ disabledi2c@ff140000rockchip,rk3399-i2clDf DX i2cpclk&default%@+ disabledi2c@ff150000rockchip,rk3399-i2clEf EY i2cpclk%default%A+ disabledi2c@ff160000rockchip,rk3399-i2clFf FZ i2cpclk$default%B+okayserial@ff180000&rockchip,rk3399-uartsnps,dw-apb-uartQ`baudclkapb_pclkc'1default %CDE disabledbluetoothbrcm,bcm43438-btFlpo >G R) d) s= default %HIJ}Kserial@ff190000&rockchip,rk3399-uartsnps,dw-apb-uartRabaudclkapb_pclkb'1default%L disabledserial@ff1a0000&rockchip,rk3399-uartsnps,dw-apb-uartSbbaudclkapb_pclkd'1default%Mokayserial@ff1b0000&rockchip,rk3399-uartsnps,dw-apb-uartTcbaudclkapb_pclke'1default%N disabledspi@ff1c0000(rockchip,rk3399-spirockchip,rk3066-spiG[spiclkapb_pclkDO O txrxdefault%PQRS+ disabledspi@ff1d0000(rockchip,rk3399-spirockchip,rk3066-spiH\spiclkapb_pclk5O O txrxdefault%TUVW+ disabledspi@ff1e0000(rockchip,rk3399-spirockchip,rk3066-spiI]spiclkapb_pclk4OOtxrxdefault%XYZ[+ disabledspi@ff1f0000(rockchip,rk3399-spirockchip,rk3066-spiJ^spiclkapb_pclkCOOtxrxdefault%\]^_+ disabledspi@ff200000(rockchip,rk3399-spirockchip,rk3066-spi K_spiclkapb_pclk`` txrxdefault%abcd/+ disabledthermal-zonescpu-thermaldetripscpu_alert0ppassivefcpu_alert1$passivegcpu_crits criticalcooling-mapsmap0fmap1gHgpu-thermaldetripsgpu_alert0$passivehgpu_crits criticalcooling-mapsmap0h itsadc@ff260000rockchip,rk3399-tsadc&alOf qOdtsadcapb_pclk tsadc-apb=sinitdefaultsleep%jk%j/okayE\eqos@ffa58000rockchip,rk3399-qossyscon sqos@ffa5c000rockchip,rk3399-qossyscon tqos@ffa60080rockchip,rk3399-qossyscon qos@ffa60100rockchip,rk3399-qossyscon qos@ffa60180rockchip,rk3399-qossyscon qos@ffa70000rockchip,rk3399-qossyscon wqos@ffa70080rockchip,rk3399-qossyscon xqos@ffa74000rockchip,rk3399-qossyscon@ uqos@ffa76000rockchip,rk3399-qossyscon` vqos@ffa90000rockchip,rk3399-qossyscon yqos@ffa98000rockchip,rk3399-qossyscon lqos@ffaa0000rockchip,rk3399-qossyscon zqos@ffaa0080rockchip,rk3399-qossyscon {qos@ffaa8000rockchip,rk3399-qossyscon |qos@ffaa8080rockchip,rk3399-qossyscon }qos@ffab0000rockchip,rk3399-qossyscon mqos@ffab0080rockchip,rk3399-qossyscon nqos@ffab8000rockchip,rk3399-qossyscon oqos@ffac0000rockchip,rk3399-qossyscon pqos@ffac0080rockchip,rk3399-qossyscon qqos@ffac8000rockchip,rk3399-qossyscon ~qos@ffac8080rockchip,rk3399-qossyscon qos@ffad0000rockchip,rk3399-qossyscon qos@ffad8080rockchip,rk3399-qossyscon qos@ffae0000rockchip,rk3399-qossyscon rpower-management@ff310000&rockchip,rk3399-pmusysconsimple-mfd1power-controller!rockchip,rk3399-power-controllerw+power-domain@34"lwpower-domain@33!mnwpower-domain@31owpower-domain@32  pqwpower-domain@35#rwpower-domain@25lwpower-domain@23swpower-domain@22ftwpower-domain@27Luwpower-domain@28vwpower-domain@8~}wpower-domain@9 wpower-domain@24wxwpower-domain@15w+power-domain@21rywpower-domain@19z{wpower-domain@20|}wpower-domain@16w+power-domain@17~wpower-domain@18wsyscon@ff320000)rockchip,rk3399-pmugrfsysconsimple-mfd2io-domains&rockchip,rk3399-pmu-io-voltage-domainokayspi@ff350000(rockchip,rk3399-spirockchip,rk3066-spi5spiclkapb_pclk<default%+ disabledserial@ff370000&rockchip,rk3399-uartsnps,dw-apb-uart7"baudclkapb_pclkf'1default% disabledi2c@ff3c0000rockchip,rk3399-i2c<l f   i2cpclk9default%+okayregulator@40silergy,syr827@default% 4` vdd_cpu_b # 8regulator-state-mem Cregulator@41silergy,syr828Adefault% 4` vdd_gpu # 8regulator-state-mem Cpmic@1brockchip,rk808xin32krtc_clko_wifi default % \ }           FregulatorsDCDC_REG1 qp vdd_center #qregulator-state-mem CDCDC_REG2 qp vdd_cpu_l #q regulator-state-mem CDCDC_REG3 vcc_ddrregulator-state-mem DCDC_REG4w@w@ vcc_1v8Kregulator-state-mem  *w@LDO_REG1w@w@ vcc1v8_camregulator-state-mem CLDO_REG2-- vcc3v0_touchregulator-state-mem CLDO_REG3w@w@ vcc1v8_pmupllregulator-state-mem  *w@LDO_REG4w@2Z vcc_sdio/regulator-state-mem  *-LDO_REG5-- vcca3v0_codecregulator-state-mem CLDO_REG6`` vcc_1v5regulator-state-mem  *`LDO_REG7w@w@ vcca1v8_codecregulator-state-mem CLDO_REG8-- vcc_3v0regulator-state-mem  *-SWITCH_REG1 vcc3v3_s3#regulator-state-mem CSWITCH_REG2 vcc3v3_s0regulator-state-mem Ci2c@ff3d0000rockchip,rk3399-i2c=l f   i2cpclk8default%+ disabledtypec-portc@22 fcs,fusb302" default% Fi2c@ff3e0000rockchip,rk3399-i2c>l f   i2cpclk:default%+ disabledpwm@ff420000(rockchip,rk3399-pwmrockchip,rk3288-pwmB Rdefault%okaypwm@ff420010(rockchip,rk3399-pwmrockchip,rk3288-pwmB Rdefault%okaypwm@ff420020(rockchip,rk3399-pwmrockchip,rk3288-pwmB  Ractive%okaypwm@ff420030(rockchip,rk3399-pwmrockchip,rk3288-pwmB0 Rdefault% disableddfi@ff630000c@rockchip,rk3399-dfiyy pclk_ddr_monvideo-codec@ff650000rockchip,rk3399-vpue rq +vepuvdpu aclkhclk ]/iommu@ff650800rockchip,iommue@s aclkiface d/video-codec@ff660000rockchip,rk3399-vdecft axiahbcabaccore ]/ iommu@ff660480rockchip,iommu f@f@u aclkiface/  diommu@ff670800rockchip,iommug@* aclkiface d disabledrga@ff680000rockchip,rk3399-rgah7maclkhclksclkjgi coreaxiahb/!efuse@ff690000rockchip,rk3399-efusei+} pclk_efusecpu-id@7cpu-leakage@17gpu-leakage@18center-leakage@19cpu-leakage@1alogic-leakage@1bwafer-info@1cdma-controller@ff6d0000arm,pl330arm,primecellm@  q | apb_pclk`dma-controller@ff6e0000arm,pl330arm,primecelln@  q | apb_pclkOclock-controller@ff750000rockchip,rk3399-pmucruuxin24m= lf(Jclock-controller@ff760000rockchip,rk3399-cruvxin24m= l@BCxDf#g/;рxh<4`#Fׄׄ ׄsyscon@ff770000&rockchip,rk3399-grfsysconsimple-mfdw+io-domains"rockchip,rk3399-io-voltage-domainokay K  / mipi-dphy-rx0rockchip,rk3399-mipi-dphy-rx0wodphy-refdphy-cfggrf/  disabledusb2phy@e450rockchip,rk3399-usb2phyP{phyclkclk_usbphy0_480mokay1host-port  +linestateokay2otg-port 0ghj+otg-bvalidotg-idlinestateokay5usb2phy@e460rockchip,rk3399-usb2phy`|phyclkclk_usbphy1_480mokay3host-port  +linestate disabled4otg-port 0lmo+otg-bvalidotg-idlinestateokay7phy@f780rockchip,rk3399-emmc-phy$emmcclk 2  disabled 0pcie-phyrockchip,rk3399-pcie-phyrefclk phyokayUflphy@ff7c0000rockchip,rk3399-typec-phy|~}tcpdcoretcpdphy-refl~f/Luphyuphy-pipeuphy-tcphy=okaydp-port 9usb3-port 6phy@ff800000rockchip,rk3399-typec-phytcpdcoretcpdphy-reflf/ Muphyuphy-pipeuphy-tcphy=okaydp-port :usb3-port 8watchdog@ff848000 rockchip,rk3399-wdtsnps,dw-wdt|xrktimer@ff850000rockchip,rk3399-timerQhZ pclktimerspdif@ff870000rockchip,rk3399-spdifB`tx mclkhclkUdefault%/ disabledi2s@ff880000(rockchip,rk3399-i2srockchip,rk3066-i2s='``txrxi2s_clki2s_hclkVbclk_onbclk_off%/ disabledi2s@ff890000(rockchip,rk3399-i2srockchip,rk3066-i2s(``txrxi2s_clki2s_hclkWdefault%/ disabledi2s@ff8a0000(rockchip,rk3399-i2srockchip,rk3066-i2s)``txrxi2s_clki2s_hclkX/okayvop@ff8f0000rockchip,rk3399-vop-lit wlfׄaclk_vopdclk_vophclk_vop ]/ axiahbdclkokayport+endpoint@0endpoint@1endpoint@2endpoint@3endpoint@4<iommu@ff8f3f00rockchip,iommu?w aclkiface/ dokayvop@ff900000rockchip,rk3399-vop-big vlfׄaclk_vopdclk_vophclk_vop ]/ axiahbdclkokayport+endpoint@0endpoint@1endpoint@2endpoint@3endpoint@4;iommu@ff903f00rockchip,iommu?v aclkiface/ dokayisp0@ff910000rockchip,rk3399-cif-isp@+nispaclkhclk ]sxdphy/ disabledports+port@0+iommu@ff914000rockchip,iommu @P+ aclkiface d/ isp1@ff920000rockchip,rk3399-cif-isp@,oispaclkhclk ]sxdphy/ disabledports+port@0+iommu@ff924000rockchip,iommu @P, aclkiface d/ hdmi-soundsimple-audio-card 1i2s J dhdmi-soundokaysimple-audio-card,cpu {simple-audio-card,codec {hdmi@ff940000rockchip,rk3399-dw-hdmi1(tqpoiahbisfrcecgrfref/=okay default%ports+port@0+endpoint@0endpoint@1port@1dsi@ff960000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi- porefpclkphy_cfggrf/apb=+ disabledports+port@0+endpoint@0endpoint@1port@1dsi@ff968000*rockchip,rk3399-mipi-dsisnps,dw-mipi-dsi. qorefpclkphy_cfggrf/apb=+  disabledports+port@0+endpoint@0endpoint@1port@1dp@ff970000rockchip,rk3399-edp jlo dppclkgrfdefault%/dp= disabledports+port@0+endpoint@0endpoint@1port@1gpu@ff9a0000#rockchip,rk3399-maliarm,mali-t8600 +jobmmugpu#2 P/#okay ipinctrlrockchip,rk3399-pinctrl=y+gpio@ff720000rockchip,gpio-bankr  )gpio@ff730000rockchip,gpio-banks  gpio@ff780000rockchip,gpio-bankxP  Ggpio@ff788000rockchip,gpio-bankxQ  $gpio@ff790000rockchip,gpio-bankyR  pcfg-pull-up pcfg-pull-down pcfg-pull-none pcfg-pull-none-12ma  pcfg-pull-none-13ma  pcfg-pull-none-18ma  pcfg-pull-none-20ma  pcfg-pull-up-2ma  pcfg-pull-up-8ma  pcfg-pull-up-18ma  pcfg-pull-up-20ma  pcfg-pull-down-4ma  pcfg-pull-down-8ma  pcfg-pull-down-12ma  pcfg-pull-down-18ma  pcfg-pull-down-20ma  pcfg-output-high pcfg-output-low pcfg-input-enable pcfg-input-pull-up  pcfg-input-pull-down  clockclk-32k cifcif-clkin  cif-clkouta  edpedp-hpd gmacrgmii-pins     rmii-pins      phy-intb   phy-rstb !i2c0i2c0-xfer i2c1i2c1-xfer =i2c2i2c2-xfer >i2c3i2c3-xfer ?i2c4i2c4-xfer   i2c5i2c5-xfer   @i2c6i2c6-xfer   Ai2c7i2c7-xfer Bi2c8i2c8-xfer i2s0i2s0-2ch-bus` i2s0-2ch-bus-bclk-off` i2s0-8ch-bus i2s0-8ch-bus-bclk-off i2s1i2s1-2ch-busP i2s1-2ch-bus-bclk-offP sdio0sdio0-bus1 sdio0-bus4@ &sdio0-cmd 'sdio0-clk (sdio0-cd sdio0-pwr sdio0-bkpwr sdio0-wp sdio0-int sdmmcsdmmc-bus1 sdmmc-bus4@    *sdmmc-clk  +sdmmc-cmd  ,sdmmc-cd sdmmc-wp sdmmc0-det-l -sdmmc0-pwr-h suspendap-pwroff ddrio-pwroff spdifspdif-bus spdif-bus-1 spi0spi0-clk Pspi0-cs0 Sspi0-cs1 spi0-tx Qspi0-rx Rspi1spi1-clk  Tspi1-cs0  Wspi1-rx Vspi1-tx Uspi2spi2-clk  Xspi2-cs0  [spi2-rx  Zspi2-tx  Yspi3spi3-clk spi3-cs0 spi3-rx spi3-tx spi4spi4-clk \spi4-cs0 _spi4-rx ^spi4-tx ]spi5spi5-clk aspi5-cs0 dspi5-rx cspi5-tx btestclktest-clkout0 test-clkout1 test-clkout2 tsadcotp-pin jotp-out kuart0uart0-xfer Cuart0-cts Euart0-rts Duart1uart1-xfer   Luart2auart2a-xfer  uart2buart2b-xfer uart2cuart2c-xfer Muart3uart3-xfer Nuart3-cts uart3-rts uart4uart4-xfer uarthdcpuarthdcp-xfer pwm0pwm0-pin pwm0-pin-pull-down vop0-pwm-pin vop1-pwm-pin pwm1pwm1-pin pwm1-pin-pull-down pwm2pwm2-pin pwm2-pin-pull-down pwm3apwm3a-pin pwm3bpwm3b-pin hdmihdmi-i2c-xfer hdmi-cec pciepci-clkreqn-cpm pci-clkreqnb-cpm fusb30xfusb0-int gpio-ledslan-led-pin sys-led-pin  wan-led-pin pmiccpu-b-sleep gpu-sleep pmic-int-l rockchip-keyreset-button-pin sdiobt-host-wake-l Ibt-reg-on-h  Hbt-wake-l Jwifi-reg_on-h  opp-table-0operating-points-v2 # opp00 .Q 5  C@opp01 .#F 5 opp02 .0, 5 P Popp03 .< 5HHopp04 .G 5B@B@opp05 .Tfr 5**opp-table-1operating-points-v2 #opp00 .Q 5  C@opp01 .#F 5 opp02 .0, 5 opp03 .< 5 Y Yopp04 .G 5~~opp05 .Tfr 5opp06 ._" 5opp07 .kI 5OOopp-table-2operating-points-v2opp00 .  5 0opp01 .@ 5 0opp02 .ׄ 5 0opp03 .e 5 Y Y0opp04 .#F 5HH0opp05 ./ 50chosen Tserial2:1500000n8external-gmac-clock fixed-clocksY@ clkin_gmacvcc3v3-sysregulator-fixed2Z2Z vcc3v3_sys 8vcc5v0-sysregulator-fixedLK@LK@ vcc5v0_sys 8vcc1v8-s3regulator-fixedw@w@ vcc1v8_s3 8Kvcc3v0-sdregulator-fixed ` s)default%-- vcc3v0_sd 8.vcca0v9-s3regulator-fixed   vcca0v9_s3 8vcca1v8-s3regulator-fixedw@w@ vcca1v8_s3 8vbus-typecregulator-fixedLK@LK@ vbus_typecgpio-keys gpio-keys xdefault%key-reset 2  reset gpio-leds gpio-ledsdefault %led-lan  green:lanled-sys )  red:power onled-wan  green:wansdio-pwrseqmmc-pwrseq-simpleF ext_clockdefault% ) %vdd-5vregulator-fixed vdd_5v compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4spi0spi1spi2spi3spi4spi5ethernet0mmc0mmc1mmc2cpudevice_typeregenable-methodcapacity-dmips-mhzclocks#cooling-cellsdynamic-power-coefficientcpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cacheoperating-points-v2cpu-supplyphandleduration-usexit-latency-uscache-levelcache-unifiedentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usmin-residency-usrockchip,pmudevfreq-eventsclock-namesstatusinterruptsarm,no-tick-in-suspendclock-frequencyclock-output-names#clock-cellsreg-names#interrupt-cellsaspm-no-l0sbus-rangeinterrupt-namesinterrupt-map-maskinterrupt-mapmax-link-speedmsi-mapphysphy-namesrangesresetsreset-namesnum-lanesvpcie0v9-supplyvpcie1v8-supplyvpcie3v3-supplyinterrupt-controllermax-functionsrockchip,max-outbound-regionspinctrl-namespinctrl-0power-domainsrockchip,grfsnps,txpblassigned-clock-parentsassigned-clocksclock_in_outphy-handlephy-modephy-supplytx_delayrx_delayreset-assert-usreset-deassert-usreset-gpiosmax-frequencyfifo-depthbus-widthcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr104assigned-clock-ratescap-mmc-highspeedcd-gpiosdisable-wpvmmc-supplyvqmmc-supplyarasan,soc-ctl-syscondisable-cqe-dcmdmmc-hs200-1_8vdr_modephy_typesnps,dis_enblslpm_quirksnps,dis-u2-freeclk-exists-quirksnps,dis_u2_susphy_quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirk#sound-dai-cellsremote-endpointmsi-controller#msi-cellsaffinity#io-channel-cellsvref-supplyi2c-scl-rising-time-nsi2c-scl-falling-time-nsreg-shiftreg-io-widthdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosmax-speedvbat-supplyvddio-supplydmasdma-namespolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#power-domain-cellspm_qospmu1830-supplyfcs,suspend-voltage-selectorregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-nameregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyregulator-on-in-suspendregulator-suspend-microvoltvbus-supply#pwm-cellsiommus#iommu-cells#dma-cellsarm,pl330-periph-burst#reset-cellsbt656-supplyaudio-supplysdmmc-supplygpio1830-supply#phy-cellsdrive-impedance-ohmrockchip,enable-strobe-pulldownrockchip,disable-mmu-resetsimple-audio-card,formatsimple-audio-card,mclk-fssimple-audio-card,namesound-daiddc-i2c-busmali-supplygpio-controller#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthoutput-highoutput-lowinput-enablerockchip,pinsopp-sharedopp-hzopp-microvoltclock-latency-nsstdout-pathenable-active-highgpioautorepeatdebounce-intervallabellinux,codedefault-state