E8d( , %,radxa,e25radxa,cm3irockchip,rk35687Radxa E25 Carrier Boardaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/mmc@fe310000/mmc@fe2b0000cpus cpu@0cpu,arm,cortex-a55 psci/<@N[h@z cpu@100cpu,arm,cortex-a55 psci/<@N[h@z cpu@200cpu,arm,cortex-a55 psci/<@N[h@z cpu@300cpu,arm,cortex-a55 psci/<@N[h@z l3-cache,cache1>@Popp-table-0,operating-points-v2opp-408000000Q  0@opp-600000000#F  0opp-8160000000,  0opp-1104000000Aʹ  0opp-1416000000Tfr  0opp-1608000000_" 0opp-1800000000kI 0opp-1992000000v 000display-subsystem,rockchip,display-subsystem disabledfirmwarescmi ,arm,scmi-smc protocol@14 opp-table-1,operating-points-v2Fopp-200000000  opp-300000000 opp-400000000ׄ opp-600000000#F opp-700000000)' opp-800000000/B@hdmi-sound,simple-audio-card-HDMIDi2s] disabledsimple-audio-card,codecwsimple-audio-card,cpuw pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24m xin32k ,fixed-clockxin32kdefault sram@10f000 ,mmio-sram sram@0,arm,scmi-shmemsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob _  sata-phy%okaysata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob `  sata-phy% disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clk3otg ;utmi_wide%DKokay  usb2-phyusb3-phydusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clk3host  usb2-phyusb3-phy ;utmi_wide%DK disabledinterrupt-controller@fd400000 ,arm,gic-v3 @F  kA(usb@fd800000 ,generic-ehci  usbokayusb@fd840000 ,generic-ohci  usbokayusb@fd880000 ,generic-ehci  usbokayusb@fd8c0000 ,generic-ohci  usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdSio-domains&,rockchip,rk3568-pmu-io-voltage-domainokay %syscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru 3clock-controller@fdd20000,rockchip,rk3568-cruxin24m 3@ PG e| i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c .- i2cpclk!default okayregulator@1c ,tcs,tcs4525vdd_cpu 50  "regulator-state-mem+pmic@20,rockchip,rk809 # default$Des%%%%%%%%%regulatorsDCDC_REG1 vdd_logic p qregulator-state-mem+DCDC_REG2vdd_gpu p qGregulator-state-mem+DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vdd_npu p qregulator-state-mem+DCDC_REG5vcc_1v8w@w@regulator-state-mem+LDO_REG1vdda0v9_image  regulator-state-mem+LDO_REG2 vdda_0v9  regulator-state-mem+LDO_REG3 vdda0v9_pmu  regulator-state-mem LDO_REG4 vccio_acodec2Z2Zregulator-state-mem+LDO_REG5 vccio_sdw@2Zregulator-state-mem+LDO_REG6 vcc3v3_pmu2Z2Zregulator-state-mem2ZLDO_REG7 vcca_1v8w@w@regulator-state-mem+LDO_REG8 vcca1v8_pmuw@w@regulator-state-memw@LDO_REG9vcca1v8_imagew@w@regulator-state-mem+SWITCH_REG1vcc_3v3regulator-state-mem+SWITCH_REG2 vcc3v3_sd[regulator-state-mem+serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t ,baudclkapb_pclk*&&'default/< disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk(defaultF disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk)defaultFokaypwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk*defaultFokaypwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk+defaultF disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controllerQ power-domain@7e,Qpower-domain@8 e-./Qpower-domain@9  e012Qpower-domain@10 e345678Qpower-domain@11 e9Qpower-domain@13 e:Qpower-domain@14 e;<=Qpower-domain@15 e>?@ABCDEQgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' ljobmmugpugpubusF%okay|Gvideo-codec@fdea0400,rockchip,rk3568-vpu lvdpu aclkhclkH% iommu@fdea0800,rockchip,rk3568-iommu@  aclkiface% Hrga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga ZaclkhclksclkD&$% coreaxiahb% video-codec@fdee0000,rockchip,rk3568-vepu @ aclkhclkI% iommu@fdee0800,rockchip,rk3568-iommu@ ? aclkiface% Immc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d biuciuciu-driveciu-sampleрDreset disabledethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a lmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refD stmmaceth| JKL disabledmdio,snps,dwmac-mdio stmmac-axi-config+Jrx-queues-config;Kqueue0tx-queues-configQLqueue0vop@fe040000 0@gvopgamma-lut (%aclkhclkdclk_vp0dclk_vp1dclk_vp2M% |  disabled,rockchip,rk3568-vopports port@0 port@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >?  aclkiface%  disabledMdsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi Dpclk dphyN% apbD|  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi Epclk dphyO% apbD|  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  -((iahbisfrcecrefdefault PQR% /| q disabledports port@0port@1qos@fe128000,rockchip,rk3568-qossyscon ,qos@fe138080,rockchip,rk3568-qossyscon ;qos@fe138100,rockchip,rk3568-qossyscon <qos@fe138180,rockchip,rk3568-qossyscon =qos@fe148000,rockchip,rk3568-qossyscon -qos@fe148080,rockchip,rk3568-qossyscon .qos@fe148100,rockchip,rk3568-qossyscon /qos@fe150000,rockchip,rk3568-qossyscon 9qos@fe158000,rockchip,rk3568-qossyscon 3qos@fe158100,rockchip,rk3568-qossyscon 4qos@fe158180,rockchip,rk3568-qossyscon 5qos@fe158200,rockchip,rk3568-qossyscon 6qos@fe158280,rockchip,rk3568-qossyscon 7qos@fe158300,rockchip,rk3568-qossyscon 8qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon >qos@fe190280,rockchip,rk3568-qossyscon Bqos@fe190300,rockchip,rk3568-qossyscon Cqos@fe190380,rockchip,rk3568-qossyscon Dqos@fe190400,rockchip,rk3568-qossyscon Eqos@fe198000,rockchip,rk3568-qossyscon :qos@fe1a8000,rockchip,rk3568-qossyscon 0qos@fe1a8080,rockchip,rk3568-qossyscon 1qos@fe1a8100,rockchip,rk3568-qossyscon 2dfi@fe230000,rockchip,rk3568-dfi#  Spcie@fe260000,rockchip,rk3568-pcie0@&gdbiapbconfig<KJIHGlsyspmcmsglegacyerr($aclk_mstaclk_slvaclk_dbipclkauxpci`TTTT  pcie-phy%T @@Dpipe okaydefaultU  V Wlegacy-interrupt-controllerk HTmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b biuciuciu-driveciu-sampleрDresetokay&0 A#Jdefault XYZUc[ommc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c biuciuciu-driveciu-sampleрDreset disabledspi@fe300000 ,rockchip,sfc0@ exvclk_sfchclk_sfc\default disabledmmc@fe310000,rockchip,rk3568-dwcmshc1 @{}P n6(|zy{}corebusaxiblocktimerokay& |default]^_`coi2s@fe400000,rockchip,rk3568-i2s-tdm@ 4@=APFqFq?C9mclk_txmclk_rxhclk*atxDPQ tx-mrx-m| q disabled i2s@fe410000,rockchip,rk3568-i2s-tdmA 5@EIPFqFqGK:mclk_txmclk_rxhclk*aarxtxDRS tx-mrx-m| default0bcdefghijklmq disabledi2s@fe420000,rockchip,rk3568-i2s-tdmB 6@MPFqOO;mclk_txmclk_rxhclk*aatxrxDTtx-m| defaultnopqq disabledi2s@fe430000,rockchip,rk3568-i2s-tdmC 7SW<mclk_txmclk_rxhclk*aatxrxDUV tx-mrx-m| q disabledpdm@fe440000,rockchip,rk3568-pdmD LZYpdm_clkpdm_hclk*a rxrstuvwdefaultDXpdm-mq disabledspdif@fe460000,rockchip,rk3568-spdifF f mclkhclk_\*atxdefaultxq disableddma-controller@fe530000,arm,pl330arm,primecellS@   apb_pclk&dma-controller@fe550000,arm,pl330arm,primecellU@  apb_pclkai2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ /HG i2cpclkydefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0JI i2cpclkzdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1LK i2cpclk{default  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2NM i2cpclk|default  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3PO i2cpclk}default  disabledwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`  tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia gRQspiclkapb_pclk*&&txrxdefault ~  disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib hTSspiclkapb_pclk*&&txrxdefault   disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic iVUspiclkapb_pclk*&&txrxdefault   disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid jXWspiclkapb_pclk*&&txrxdefault   disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte ubaudclkapb_pclk*&&default/< disabledserial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v# baudclkapb_pclk*&&default/<okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w'$baudclkapb_pclk*&&default/< disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x+(baudclkapb_pclk*&& default/< disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y/,baudclkapb_pclk*& & default/< disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z30baudclkapb_pclk*& & default/< disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk {74baudclkapb_pclk*&&default/< disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl |;8baudclkapb_pclk*&&default/< disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm }?<baudclkapb_pclk*&&default/< disabledthermal-zonescpu-thermaldtripscpu_alert0ppassivecpu_alert1$passivecpu_crits criticalcooling-mapsmap0 0  gpu-thermaltripsgpu-thresholdppassivegpu-target$passivegpu-crits criticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq s@Pf@ `tsadcapb_pclkD|  sinitdefaultsleep , 6 @okay V msaradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]saradcapb_pclkD saradc-apb okay pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultF disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultF disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultF disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaultF disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultF disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultF disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaultF disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaultF disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultFokaypwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultF disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultF disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaultF disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipe@"PD   okay phy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipe@%PD   okayphy@fe870000,rockchip,rk3568-csi-dphyypclk Dapb|  disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz % apbD disabledNmipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ % apbD disabledOusb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m   okayhost-port  disabledotg-port okay usb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m   okayhost-port okay otg-port okay pinctrl,rockchip,rk3568-pinctrl| S gpio@fdd60000,rockchip,gpio-bank !.     k#gpio@fe740000,rockchip,gpio-bankt "cd    kVgpio@fe750000,rockchip,gpio-banku #ef  @  kgpio@fe760000,rockchip,gpio-bankv $gh  `  kgpio@fe770000,rockchip,gpio-bankw %ij    kpcfg-pull-up pcfg-pull-none )pcfg-pull-none-drv-level-1 ) 6pcfg-pull-none-drv-level-2 ) 6pcfg-pull-none-drv-level-3 ) 6pcfg-pull-up-drv-level-1  6pcfg-pull-up-drv-level-2  6pcfg-pull-none-smt ) Eacodecaudiopwmbt656bt1120camcan0can1can2cifclk32kclk32k-out0 Zcpuebcedpdpemmcemmc-bus8 Z  ]emmc-clk Z^emmc-cmd Z_emmc-datastrobe Z`eth0eth1flashfspifspi-pins` Z\gmac0gmac1gpuhdmitxhdmitxm0-cec ZRhdmitx-scl ZPhdmitx-sda ZQi2c0i2c0-xfer Z  !i2c1i2c1-xfer Z  yi2c2i2c2m0-xfer Z zi2c3i2c3m0-xfer Z{i2c4i2c4m0-xfer Z  |i2c5i2c5m0-xfer Z  }i2s1i2s1m0-lrckrx Zei2s1m0-lrcktx Zdi2s1m0-sclkrx Zci2s1m0-sclktx Zbi2s1m0-sdi0 Z fi2s1m0-sdi1 Z gi2s1m0-sdi2 Z hi2s1m0-sdi3 Zii2s1m0-sdo0 Zji2s1m0-sdo1 Zki2s1m0-sdo2 Z li2s1m0-sdo3 Z mi2s2i2s2m0-lrcktx Zoi2s2m0-sclktx Zni2s2m0-sdi Zpi2s2m0-sdo Zqi2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x1m0-pins0 Zpcie30x2pdmpdmm0-clk Zrpdmm0-clk1 Zspdmm0-sdi0 Z tpdmm0-sdi1 Z updmm0-sdi2 Z vpdmm0-sdi3 Zwpmicpmic_int Z$pmupwm0pwm0m0-pins Z(pwm1pwm1m0-pins Z)pwm2pwm2m0-pins Z*pwm3pwm3-pins Z+pwm4pwm4-pins Zpwm5pwm5-pins Zpwm6pwm6-pins Zpwm7pwm7-pins Zpwm8pwm8m0-pins Z pwm9pwm9m0-pins Z pwm10pwm10m0-pins Z pwm11pwm11m0-pins Zpwm12pwm12m1-pins Zpwm13pwm13m0-pins Zpwm14pwm14m0-pins Zpwm15pwm15m0-pins Zrefclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ZXsdmmc0-clk ZYsdmmc0-cmd ZZsdmmc1sdmmc2spdifspdifm0-tx Zxspi0spi0m0-pins0 Z spi0m0-cs0 Z~spi0m0-cs1 Zspi1spi1m0-pins0 Z spi1m0-cs0 Zspi1m0-cs1 Zspi2spi2m0-pins0 Zspi2m0-cs0 Zspi2m0-cs1 Zspi3spi3m0-pins0 Z  spi3m0-cs0 Zspi3m0-cs1 Ztsadctsadc-shutorg Ztsadc-pin Zuart0uart0-xfer Z'uart1uart1m0-xfer Z  uart2uart2m0-xfer Zuart3uart3m0-xfer Zuart4uart4m0-xfer Zuart5uart5m0-xfer Zuart6uart6m0-xfer Zuart7uart7m0-xfer Zuart8uart8m0-xfer Zuart9uart9m0-xfer Zvopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2ledsled_user_en Zpciepcie20-reset-h Z Upcie30x1-enable-h Zpcie30x2-reset-h Zpcie-enable-h Zusbminipcie-enable-h Zngffpcie-enable-h Zvbus_typec_en Zsata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob ^  sata-phy% disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconqos@fe190080,rockchip,rk3568-qossyscon ?qos@fe190100,rockchip,rk3568-qossyscon @qos@fe190200,rockchip,rk3568-qossyscon Asyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀphy@fe8c0000,rockchip,rk3568-pcie3-phy &'wrefclk_mrefclk_npclkDphy hokay ypcie@fe270000,rockchip,rk3568-pcie ($aclk_mstaclk_slvaclk_dbipclkauxpci<lsyspmcmsglegacyerr`  pcie-phy%0@@'T @@@gdbiapbconfigDpipeokaydefault  #legacy-interrupt-controllerk pcie@fe280000,rockchip,rk3568-pcie ($aclk_mstaclk_slvaclk_dbipclkauxpci<lsyspmcmsglegacyerr`   pcie-phy%0@(T @@gdbiapbconfigDpipeokaydefault  Wlegacy-interrupt-controllerk ethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*lmacirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refD stmmaceth|  disabledmdio,snps,dwmac-mdio stmmac-axi-config+rx-queues-config;queue0tx-queues-configQqueue0phy@fe820000,rockchip,rk3568-naneng-combphy| refapbpipe@PD   okaychosen serial2:115200n8gpio-leds ,gpio-ledsled-0 # heartbeat  heartbeatdefaultpcie30-avdd0v9-regulator,regulator-fixedpcie30_avdd0v9   %pcie30-avdd1v8-regulator,regulator-fixedpcie30_avdd1v8w@w@ %vcc3v3-sys-regulator,regulator-fixed vcc3v3_sys2Z2Z "%vcc5v0-sys-regulator,regulator-fixed vcc5v0_sysLK@LK@ "vcc5v-input-regulator,regulator-fixed vcc5v_inputLK@LK@"pwm-leds,pwm-leds-multicolormulti-led  led-red  B@led-green  B@led-blue  B@vbus-typec-regulator,regulator-fixed  #default vbus_typecLK@LK@ vcc3v3-minipcie-regulator,regulator-fixed  defaultvcc3v3_minipcie2Z2Z Wvcc3v3-ngff-regulator,regulator-fixed  #default vcc3v3_ngff2Z2Z vcc3v3-pcie30x1-regulator,regulator-fixed  #defaultvcc3v3_pcie30x12Z2Z vcc3v3-pi6c-05-regulator,regulator-fixed  #default vcc3v3_pcie2Z2Z W interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3mmc0mmc1device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsstatusarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fssound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controllerwakeup-sourcevcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-names#sound-dai-cellsrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesreset-gpiosvpcie3v3-supplybus-widthcap-sd-highspeedcd-gpiosdisable-wpsd-uhs-sdr104vmmc-supplyvqmmc-supplynon-removabledma-namesarm,pl330-periph-burst#dma-cellspolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsphy-supplyrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfdata-lanesstdout-pathfunctioncolorlinux,default-triggermax-brightnesspwmsenable-active-highgpio