_8(  ,radxa,rock3arockchip,rk35687Radxa ROCK 3Aaliases=/pinctrl/gpio@fdd60000C/pinctrl/gpio@fe740000I/pinctrl/gpio@fe750000O/pinctrl/gpio@fe760000U/pinctrl/gpio@fe770000[/i2c@fdd40000`/i2c@fe5a0000e/i2c@fe5b0000j/i2c@fe5c0000o/i2c@fe5d0000t/i2c@fe5e0000y/serial@fdd50000/serial@fe650000/serial@fe660000/serial@fe670000/serial@fe680000/serial@fe690000/serial@fe6a0000/serial@fe6b0000/serial@fe6c0000/serial@fe6d0000/spi@fe610000/spi@fe620000/spi@fe630000/spi@fe640000/ethernet@fe010000/mmc@fe310000/mmc@fe2b0000/mmc@fe000000cpus cpu@0cpu,arm,cortex-a55 psci*>K@]jw@ cpu@100cpu,arm,cortex-a55 psci*>K@]jw@ cpu@200cpu,arm,cortex-a55 psci*>K@]jw@ cpu@300cpu,arm,cortex-a55 psci*>K@]jw@ l3-cache,cache@M@_opp-table-0,operating-points-v2opp-408000000Q  0@opp-600000000#F  0opp-8160000000,  0opp-1104000000Aʹ  0opp-1416000000Tfr  0opp-1608000000_" 0opp-1800000000kI 0opp-1992000000v 000display-subsystem,rockchip,display-subsystemfirmwarescmi ,arm,scmi-smc" protocol@14(opp-table-1,operating-points-v2Gopp-200000000  opp-300000000 opp-400000000ׄ opp-600000000#F opp-700000000)' opp-800000000/B@hdmi-sound,simple-audio-card5HDMILi2seokaysimple-audio-card,codecsimple-audio-card,cpu pmu,arm,cortex-a55-pmu0 psci ,arm,psci-1.0#smctimer,arm,armv8-timer0   xin24m ,fixed-clockn6xin24m(xin32k ,fixed-clockxin32kdefault(sram@10f000 ,mmio-sram sram@0,arm,scmi-shmemsata@fc400000',rockchip,rk3568-dwc-ahcisnps,dwc-ahci@satapmaliverxoob _ sata-phy"4 disabledsata@fc800000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob ` sata-phy"4 disabledusb@fcc00000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clkBotg Jutmi_wide4SZokay usb2-phyusb3-physusb@fd000000,rockchip,rk3568-dwc3snps,dwc3@ ref_clksuspend_clkbus_clkBhost usb2-phyusb3-phy Jutmi_wide4SZokayinterrupt-controller@fd400000 ,arm,gic-v3 @F  zA(usb@fd800000 ,generic-ehci usbokayusb@fd840000 ,generic-ohci usbokayusb@fd880000 ,generic-ehci usbokayusb@fd8c0000 ,generic-ohci usbokaysyscon@fdc20000),rockchip,rk3568-pmugrfsysconsimple-mfdgio-domains&,rockchip,rk3568-pmu-io-voltage-domainokay &4syscon@fdc50000 ,rockchip,rk3568-pipe-grfsysconsyscon@fdc60000&,rockchip,rk3568-grfsysconsimple-mfd syscon@fdc80000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdc90000$,rockchip,rk3568-pipe-phy-grfsysconsyscon@fdca0000#,rockchip,rk3568-usb2phy-grfsysconsyscon@fdca8000#,rockchip,rk3568-usb2phy-grfsysconʀclock-controller@fdd00000,rockchip,rk3568-pmucru(Bclock-controller@fdd20000,rockchip,rk3568-cruxin24m(BO _G t i2c@fdd40000(,rockchip,rk3568-i2crockchip,rk3399-i2c .- i2cpclk!default okayregulator@1c ,tcs,tcs4525vdd_cpu 50/"regulator-state-mem:pmic@20,rockchip,rk809 #OHt(mclkHdefault$%St&&&&&&&&&regulatorsDCDC_REG1 vdd_logic pqregulator-state-mem:DCDC_REG2vdd_gpu pqHregulator-state-mem:DCDC_REG3vcc_ddrregulator-state-memDCDC_REG4vdd_npu pqregulator-state-mem:DCDC_REG5vcc_1v8w@w@regulator-state-mem:LDO_REG1vdda0v9_image  cregulator-state-mem:LDO_REG2 vdda_0v9  regulator-state-mem:LDO_REG3 vdda0v9_pmu  regulator-state-mem. LDO_REG4 vccio_acodec2Z2Zregulator-state-mem:LDO_REG5 vccio_sdw@2Zregulator-state-mem:LDO_REG6 vcc3v3_pmu2Z2Zregulator-state-mem.2ZLDO_REG7 vcca_1v8w@w@regulator-state-mem:LDO_REG8 vcca1v8_pmuw@w@regulator-state-mem.w@LDO_REG9vcca1v8_imagew@w@dregulator-state-mem:SWITCH_REG1vcc_3v3regulator-state-mem:SWITCH_REG2 vcc3v3_sdoregulator-state-mem:serial@fdd50000&,rockchip,rk3568-uartsnps,dw-apb-uart t ,baudclkapb_pclkJ''(defaultO\ disabledpwm@fdd70000(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk)defaultf disabledpwm@fdd70010(,rockchip,rk3568-pwmrockchip,rk3328-pwm 0 pwmpclk*defaultf disabledpwm@fdd70020(,rockchip,rk3568-pwmrockchip,rk3328-pwm  0 pwmpclk+defaultf disabledpwm@fdd70030(,rockchip,rk3568-pwmrockchip,rk3328-pwm0 0 pwmpclk,defaultf disabledpower-management@fdd90000&,rockchip,rk3568-pmusysconsimple-mfdpower-controller!,rockchip,rk3568-power-controllerq power-domain@7-qpower-domain@8 ./0qpower-domain@9  123qpower-domain@10 456789qpower-domain@11 :qpower-domain@13 ;qpower-domain@14 <=>qpower-domain@15 ?@ABCDEFqgpu@fde60000&,rockchip,rk3568-maliarm,mali-bifrost@$()' jobmmugpugpubus *G4okayHvideo-codec@fdea0400,rockchip,rk3568-vpu vdpu aclkhclkI4 iommu@fdea0800,rockchip,rk3568-iommu@  aclkiface4 Irga@fdeb0000(,rockchip,rk3568-rgarockchip,rk3288-rga ZaclkhclksclkS&$% coreaxiahb4 video-codec@fdee0000,rockchip,rk3568-vepu @ aclkhclkJ4 iommu@fdee0800,rockchip,rk3568-iommu@ ? aclkiface4 Jmmc@fe0000000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc@ d biuciuciu-driveciu-sampleрSresetokay*K5default LMNCP]jx&ethernet@fe010000&,rockchip,rk3568-gmacsnps,dwmac-4.20a macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refS stmmaceth OPQokayO tRinputS rgmii-iddefaultTUVWXYmdio,snps,dwmac-mdio ethernet-phy@0,ethernet-phy-ieee802.3-c22defaultZ N  /[Sstmmac-axi-config;EUOrx-queues-configePqueue0tx-queues-config{Qqueue0vop@fe040000 0@vopgamma-lut (%aclkhclkdclk_vp0dclk_vp1dclk_vp2\4  okay,rockchip,rk3568-vopOtports port@0 endpoint@2]eport@1 port@2 iommu@fe043e00,rockchip,rk3568-iommu >?  aclkiface4 okay\dsi@fe060000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi Dpclkdphy^4 apbS  disabledports port@0port@1dsi@fe070000*,rockchip,rk3568-mipi-dsisnps,dw-mipi-dsi Epclkdphy_4 apbS  disabledports port@0port@1hdmi@fe0a0000,rockchip,rk3568-dw-hdmi  -((iahbisfrcecrefdefault `ab4 O tokaycdports port@0endpointe]port@1endpointfqos@fe128000,rockchip,rk3568-qossyscon -qos@fe138080,rockchip,rk3568-qossyscon <qos@fe138100,rockchip,rk3568-qossyscon =qos@fe138180,rockchip,rk3568-qossyscon >qos@fe148000,rockchip,rk3568-qossyscon .qos@fe148080,rockchip,rk3568-qossyscon /qos@fe148100,rockchip,rk3568-qossyscon 0qos@fe150000,rockchip,rk3568-qossyscon :qos@fe158000,rockchip,rk3568-qossyscon 4qos@fe158100,rockchip,rk3568-qossyscon 5qos@fe158180,rockchip,rk3568-qossyscon 6qos@fe158200,rockchip,rk3568-qossyscon 7qos@fe158280,rockchip,rk3568-qossyscon 8qos@fe158300,rockchip,rk3568-qossyscon 9qos@fe180000,rockchip,rk3568-qossyscon qos@fe190000,rockchip,rk3568-qossyscon ?qos@fe190280,rockchip,rk3568-qossyscon Cqos@fe190300,rockchip,rk3568-qossyscon Dqos@fe190380,rockchip,rk3568-qossyscon Eqos@fe190400,rockchip,rk3568-qossyscon Fqos@fe198000,rockchip,rk3568-qossyscon ;qos@fe1a8000,rockchip,rk3568-qossyscon 1qos@fe1a8080,rockchip,rk3568-qossyscon 2qos@fe1a8100,rockchip,rk3568-qossyscon 3dfi@fe230000,rockchip,rk3568-dfi#  gpcie@fe260000,rockchip,rk3568-pcie0@&dbiapbconfig<KJIHGsyspmcmsglegacyerr($aclk_mstaclk_slvaclk_dbipclkauxpci`hhhh   # 2 A I pcie-phy4T @@Spipe okaydefaulti /[ Sjlegacy-interrupt-controllerz Hhmmc@fe2b00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc+@ b biuciuciu-driveciu-sampleрSresetokay c#defaultklmn]xommc@fe2c00000,rockchip,rk3568-dw-mshcrockchip,rk3288-dw-mshc,@ c biuciuciu-driveciu-sampleрSreset disabledspi@fe300000 ,rockchip,sfc0@ exvclk_sfchclk_sfcpdefaultokay flash@0,jedec,spi-nor l2 ~ mmc@fe310000,rockchip,rk3568-dwcmshc1 O{}_ n6(|zy{}corebusaxiblocktimerokay 5defaultqrstxi2s@fe400000,rockchip,rk3568-i2s-tdm@ 4O=A_FqFq?C9mclk_txmclk_rxhclkJu txSPQ tx-mrx-m tokay i2s@fe410000,rockchip,rk3568-i2s-tdmA 5OEI_FqFqGK:mclk_txmclk_rxhclkJuu rxtxSRS tx-mrx-m defaultvwxytokay i2s@fe420000,rockchip,rk3568-i2s-tdmB 6OM_FqOO;mclk_txmclk_rxhclkJuu txrxSTtx-m defaultz{|}tokay i2s@fe430000,rockchip,rk3568-i2s-tdmC 7SW<mclk_txmclk_rxhclkJuu txrxSUV tx-mrx-m t disabledpdm@fe440000,rockchip,rk3568-pdmD LZYpdm_clkpdm_hclkJu  rx~defaultSXpdm-mt disabledspdif@fe460000,rockchip,rk3568-spdifF f mclkhclk_\Ju txdefaultt disableddma-controller@fe530000,arm,pl330arm,primecellS@    apb_pclk 'dma-controller@fe550000,arm,pl330arm,primecellU@   apb_pclk ui2c@fe5a0000(,rockchip,rk3568-i2crockchip,rk3399-i2cZ /HG i2cpclkdefault  disabledi2c@fe5b0000(,rockchip,rk3568-i2crockchip,rk3399-i2c[ 0JI i2cpclkdefault  disabledi2c@fe5c0000(,rockchip,rk3568-i2crockchip,rk3399-i2c\ 1LK i2cpclkdefault  disabledi2c@fe5d0000(,rockchip,rk3568-i2crockchip,rk3399-i2c] 2NM i2cpclkdefault  disabledi2c@fe5e0000(,rockchip,rk3568-i2crockchip,rk3399-i2c^ 3PO i2cpclkdefault okayrtc@51,haoyu,hym8563Q#( rtcic_32koutdefaultwatchdog@fe600000 ,rockchip,rk3568-wdtsnps,dw-wdt`  tclkpclkspi@fe610000(,rockchip,rk3568-spirockchip,rk3066-spia gRQspiclkapb_pclkJ'' txrxdefault   disabledspi@fe620000(,rockchip,rk3568-spirockchip,rk3066-spib hTSspiclkapb_pclkJ'' txrxdefault   disabledspi@fe630000(,rockchip,rk3568-spirockchip,rk3066-spic iVUspiclkapb_pclkJ'' txrxdefault   disabledspi@fe640000(,rockchip,rk3568-spirockchip,rk3066-spid jXWspiclkapb_pclkJ'' txrxdefault   disabledserial@fe650000&,rockchip,rk3568-uartsnps,dw-apb-uarte ubaudclkapb_pclkJ'' defaultO\okay bluetooth,brcm,bcm43438-btlpo    default  ,& 8serial@fe660000&,rockchip,rk3568-uartsnps,dw-apb-uartf v# baudclkapb_pclkJ''defaultO\okayserial@fe670000&,rockchip,rk3568-uartsnps,dw-apb-uartg w'$baudclkapb_pclkJ''defaultO\ disabledserial@fe680000&,rockchip,rk3568-uartsnps,dw-apb-uarth x+(baudclkapb_pclkJ'' defaultO\ disabledserial@fe690000&,rockchip,rk3568-uartsnps,dw-apb-uarti y/,baudclkapb_pclkJ' ' defaultO\ disabledserial@fe6a0000&,rockchip,rk3568-uartsnps,dw-apb-uartj z30baudclkapb_pclkJ' ' defaultO\ disabledserial@fe6b0000&,rockchip,rk3568-uartsnps,dw-apb-uartk {74baudclkapb_pclkJ''defaultO\ disabledserial@fe6c0000&,rockchip,rk3568-uartsnps,dw-apb-uartl |;8baudclkapb_pclkJ''defaultO\ disabledserial@fe6d0000&,rockchip,rk3568-uartsnps,dw-apb-uartm }?<baudclkapb_pclkJ''defaultO\ disabledthermal-zonescpu-thermal Ed [ itripscpu_alert0 yp passivecpu_alert1 y$ passivecpu_crit ys  criticalcooling-mapsmap0 0 gpu-thermal E [ itripsgpu-threshold yp passivegpu-target y$ passivegpu-crit ys  criticalcooling-mapsmap0  tsadc@fe710000,rockchip,rk3568-tsadcq sO_f@ `tsadcapb_pclkS  sinitdefaultsleep   okay  saradc@fe720000.,rockchip,rk3568-saradcrockchip,rk3399-saradcr ]saradcapb_pclkS saradc-apb okay )pwm@fe6e0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultf disabledpwm@fe6e0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmnZY pwmpclkdefaultf disabledpwm@fe6e0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmn ZY pwmpclkdefaultf disabledpwm@fe6e0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmn0ZY pwmpclkdefaultf disabledpwm@fe6f0000(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultf disabledpwm@fe6f0010(,rockchip,rk3568-pwmrockchip,rk3328-pwmo]\ pwmpclkdefaultf disabledpwm@fe6f0020(,rockchip,rk3568-pwmrockchip,rk3328-pwmo ]\ pwmpclkdefaultf disabledpwm@fe6f0030(,rockchip,rk3568-pwmrockchip,rk3328-pwmo0]\ pwmpclkdefaultf disabledpwm@fe700000(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultf disabledpwm@fe700010(,rockchip,rk3568-pwmrockchip,rk3328-pwmp`_ pwmpclkdefaultf disabledpwm@fe700020(,rockchip,rk3568-pwmrockchip,rk3328-pwmp `_ pwmpclkdefaultf disabledpwm@fe700030(,rockchip,rk3568-pwmrockchip,rk3328-pwmp0`_ pwmpclkdefaultf disabledphy@fe830000,rockchip,rk3568-naneng-combphy"} refapbpipeO"_S 5 G ]okayphy@fe840000,rockchip,rk3568-naneng-combphy%~ refapbpipeO%_S 5 G ]okayphy@fe870000,rockchip,rk3568-csi-dphyypclk ]Sapb  disabledmipi-dphy@fe850000,rockchip,rk3568-dsi-dphy refpclkz ]4 apbS disabled^mipi-dphy@fe860000,rockchip,rk3568-dsi-dphy refpclk{ ]4 apbS disabled_usb2phy@fe8a0000,rockchip,rk3568-usb2phyphyclkclk_usbphy0_480m  h(okayhost-port ]okayotg-port ]okayusb2phy@fe8b0000,rockchip,rk3568-usb2phyphyclkclk_usbphy1_480m  h(okayhost-port ]okayotg-port ]okaypinctrl,rockchip,rk3568-pinctrl g gpio@fdd60000,rockchip,gpio-bank !.  x  z#gpio@fe740000,rockchip,gpio-bankt "cd x  zgpio@fe750000,rockchip,gpio-banku #ef x @  zgpio@fe760000,rockchip,gpio-bankv $gh x `  z[gpio@fe770000,rockchip,gpio-bankw %ij x  zpcfg-pull-up pcfg-pull-down pcfg-pull-none pcfg-pull-none-drv-level-1  pcfg-pull-none-drv-level-2  pcfg-pull-none-drv-level-3  pcfg-pull-up-drv-level-1  pcfg-pull-up-drv-level-2  pcfg-pull-none-smt  acodecaudiopwmbt656bt1120camvcc_cam_en  can0can1can2cifclk32kclk32k-out0 cpuebcedpdpemmcemmc-bus8   qemmc-clk remmc-cmd semmc-datastrobe teth0eth1flashfspifspi-pins` pgmac0gmac1gmac1m1-miim Tgmac1m1-clkinout Xgmac1m1-rx-bus20  Vgmac1m1-tx-bus20 Ugmac1m1-rgmii-clk Wgmac1m1-rgmii-bus@ Ygpuhdmitxhdmitxm1-cec bhdmitx-scl `hdmitx-sda ai2c0i2c0-xfer  !i2c1i2c1-xfer  i2c2i2c2m0-xfer i2c3i2c3m1-xfer  i2c4i2c4m1-xfer   i2c5i2c5m0-xfer   i2s1i2s1m0-lrcktx wi2s1m0-mclk %i2s1m0-sclktx vi2s1m0-sdi0  xi2s1m0-sdo0 yi2s2i2s2m0-lrcktx {i2s2m0-sclktx zi2s2m0-sdi |i2s2m0-sdo }i2s3ispjtaglcdcmcunpupcie20pcie30x1pcie30x2pcie30x2m1-pins0 pdmpdmm0-clk ~pdmm0-clk1 pdmm0-sdi0  pdmm0-sdi1  pdmm0-sdi2  pdmm0-sdi3 pmicpmic_int $pmupwm0pwm0m0-pins )pwm1pwm1m0-pins *pwm2pwm2m0-pins +pwm3pwm3-pins ,pwm4pwm4-pins pwm5pwm5-pins pwm6pwm6-pins pwm7pwm7-pins pwm8pwm8m0-pins  pwm9pwm9m0-pins  pwm10pwm10m0-pins  pwm11pwm11m0-pins pwm12pwm12m0-pins pwm13pwm13m0-pins pwm14pwm14m0-pins pwm15pwm15m0-pins refclksatasata0sata1sata2scrsdmmc0sdmmc0-bus4@ ksdmmc0-clk lsdmmc0-cmd msdmmc0-det nsdmmc1sdmmc2sdmmc2m0-bus4@ Lsdmmc2m0-clk Nsdmmc2m0-cmd Mspdifspdifm0-tx spi0spi0m0-pins0 spi0m0-cs0 spi0m0-cs1 spi1spi1m0-pins0  spi1m0-cs0 spi1m0-cs1 spi2spi2m0-pins0 spi2m0-cs0 spi2m0-cs1 spi3spi3m0-pins0   spi3m0-cs0 spi3m0-cs1 tsadctsadc-shutorg tsadc-pin uart0uart0-xfer (uart1uart1m0-xfer   uart1m0-ctsn uart1m0-rtsn  uart2uart2m0-xfer uart3uart3m0-xfer uart4uart4m0-xfer uart5uart5m0-xfer uart6uart6m0-xfer uart7uart7m0-xfer uart8uart8m0-xfer uart9uart9m0-xfer vopspi0-hsspi1-hsspi2-hsspi3-hsgmac-txd-level3gmac-txc-level2displayvcc_mipi_en etherneteth_phy_rst Zhym8563hym8563-int ledsled_user_en pciepcie-enable-h pcie-reset-h iusbvcc5v0_usb_host_en vcc5v0_usb_hub_en vcc5v0_usb_otg_en btbt-enable  bt-host-wake  bt-wake  sdio-pwrseqwifi-enable sata@fc000000',rockchip,rk3568-dwc-ahcisnps,dwc-ahcisatapmaliverxoob ^ sata-phy"4 disabledsyscon@fdc70000$,rockchip,rk3568-pipe-phy-grfsysconqos@fe190080,rockchip,rk3568-qossyscon @qos@fe190100,rockchip,rk3568-qossyscon Aqos@fe190200,rockchip,rk3568-qossyscon Bsyscon@fdcb8000%,rockchip,rk3568-pcie3-phy-grfsysconˀphy@fe8c0000,rockchip,rk3568-pcie3-phy ]&'wrefclk_mrefclk_npclkSphy okaypcie@fe270000,rockchip,rk3568-pcie ($aclk_mstaclk_slvaclk_dbipclkauxpci<syspmcmsglegacyerr`   # 2 A I pcie-phy40@@'T @@@dbiapbconfigSpipe disabledlegacy-interrupt-controllerz pcie@fe280000,rockchip,rk3568-pcie ($aclk_mstaclk_slvaclk_dbipclkauxpci<syspmcmsglegacyerr`   # 2 A  I pcie-phy40@(T @@dbiapbconfigSpipeokaydefault / Sjlegacy-interrupt-controllerz ethernet@fe2a0000&,rockchip,rk3568-gmacsnps,dwmac-4.20a*macirqeth_wake_irq@Wstmmacethmac_clk_rxmac_clk_txclk_mac_refoutaclk_macpclk_macclk_mac_speedptp_refS stmmaceth  disabledmdio,snps,dwmac-mdio stmmac-axi-config;EUrx-queues-configequeue0tx-queues-config{queue0phy@fe820000,rockchip,rk3568-naneng-combphy| refapbpipeO_S 5 G ]okaychosen serial2:1500000n8hdmi-con,hdmi-connectoraportendpointfexternal-gmac1-clock ,fixed-clocksY@ gmac1_clkin(Rleds ,gpio-ledsled-0 5# heartbeat ! 'heartbeatdefaultrk809-sound,simple-audio-cardLi2s 5Analog RK809esimple-audio-card,cpusimple-audio-card,codecsdio-pwrseq,mmc-pwrseq-simple ext_clockdefault =d TLK@ /[Kvcc12v-dcin-regulator,regulator-fixed vcc12v_dcinpcie30-avdd0v9-regulator,regulator-fixedpcie30_avdd0v9  /&pcie30-avdd1v8-regulator,regulator-fixedpcie30_avdd1v8w@w@/&vcc3v3-pi6c-03-regulator,regulator-fixedvcc3v3_pi6c_032Z2Z/"vcc3v3-pcie-regulator,regulator-fixed g 5#default vcc3v3_pcie2Z2Z/"jvcc3v3-sys-regulator,regulator-fixed vcc3v3_sys2Z2Z/&vcc5v0-sys-regulator,regulator-fixed vcc5v0_sysLK@LK@/"vcc5v0-usb-regulator,regulator-fixed vcc5v0_usbLK@LK@/vcc5v0-usb-host-regulator,regulator-fixed g z#defaultvcc5v0_usb_hostLK@LK@/vcc5v0-usb-hub-regulator,regulator-fixed g z#defaultvcc5v0_usb_hub/vcc5v0-usb-otg-regulator,regulator-fixed g z#defaultvcc5v0_usb_otgLK@LK@/vcc-cam-regulator,regulator-fixed g z defaultvcc_cam2Z2Z/&regulator-state-mem:vcc-mipi-regulator,regulator-fixed g z[default vcc_mipi2Z2Z/&regulator-state-mem: interrupt-parent#address-cells#size-cellscompatiblemodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3ethernet0mmc0mmc1mmc2device_typeregclocks#cooling-cellsenable-methodoperating-points-v2i-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachecpu-supplyphandlecache-levelcache-unifiedopp-sharedopp-hzopp-microvoltclock-latency-nsopp-suspendportsarm,smc-idshmem#clock-cellssimple-audio-card,namesimple-audio-card,formatsimple-audio-card,mclk-fsstatussound-daiinterruptsinterrupt-affinityarm,no-tick-in-suspendclock-frequencyclock-output-namespinctrl-0pinctrl-namesrangesclock-namesphysphy-namesports-implementedpower-domainsdr_modephy_typeresetssnps,dis_u2_susphy_quirkextconinterrupt-controller#interrupt-cellsmbi-aliasmbi-rangesmsi-controllerpmuio1-supplypmuio2-supplyvccio1-supplyvccio2-supplyvccio3-supplyvccio4-supplyvccio5-supplyvccio6-supplyvccio7-supply#reset-cellsassigned-clocksassigned-clock-ratesassigned-clock-parentsrockchip,grffcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspendrockchip,system-power-controller#sound-dai-cellsvcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplywakeup-sourceregulator-initial-moderegulator-on-in-suspendregulator-suspend-microvoltdmasreg-io-widthreg-shift#pwm-cells#power-domain-cellspm_qosinterrupt-namesmali-supplyiommus#iommu-cellsreset-namesfifo-depthmax-frequencybus-widthdisable-wpcap-sd-highspeedcap-sdio-irqkeep-power-in-suspendmmc-pwrseqnon-removablesd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-sdr104vmmc-supplyvqmmc-supplysnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsoclock_in_outphy-handlephy-modephy-supplyreset-assert-usreset-deassert-usreset-gpiossnps,blensnps,rd_osr_lmtsnps,wr_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-usereg-namesremote-endpointavdd-0v9-supplyavdd-1v8-supplyrockchip,pmubus-rangeinterrupt-map-maskinterrupt-maplinux,pci-domainnum-ib-windowsnum-ob-windowsmax-link-speedmsi-mapnum-lanesvpcie3v3-supplycd-gpiosspi-max-frequencyspi-rx-bus-widthspi-tx-bus-widthdma-namesrockchip,trcm-sync-tx-onlyarm,pl330-periph-burst#dma-cellsuart-has-rtsctsdevice-wakeup-gpioshost-wakeup-gpiosshutdown-gpiosvbat-supplyvddio-supplypolling-delay-passivepolling-delaythermal-sensorstemperaturehysteresistripcooling-devicerockchip,hw-tshut-temppinctrl-1pinctrl-2#thermal-sensor-cellsrockchip,hw-tshut-moderockchip,hw-tshut-polarity#io-channel-cellsvref-supplyrockchip,pipe-grfrockchip,pipe-phy-grf#phy-cellsrockchip,usbgrfgpio-controllergpio-ranges#gpio-cellsbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsrockchip,phy-grfstdout-pathfunctioncolorlinux,default-triggerpost-power-on-delay-mspower-off-delay-usenable-active-highgpio