58(H( ("tsd,rk3588-jaguarrockchip,rk3588 +$7Theobroma Systems RK3588-SBC Jaguaraliases=/pinctrl/gpio@fd8a0000C/pinctrl/gpio@fec20000I/pinctrl/gpio@fec30000O/pinctrl/gpio@fec40000U/pinctrl/gpio@fec50000[/i2c@fd880000`/i2c@fea90000e/i2c@feaa0000j/i2c@feab0000o/i2c@feac0000t/i2c@fead0000y/i2c@fec80000~/i2c@fec90000/i2c@feca0000/serial@fd890000/serial@feb40000/serial@feb50000/serial@feb60000/serial@feb70000/serial@feb80000/serial@feb90000/serial@feba0000/serial@febb0000/serial@febc0000/spi@feb00000/spi@feb10000/spi@feb20000/spi@feb30000/spi@fecb0000/ethernet@fe1b0000/mmc@fe2e0000/mmc@fe2c0000/i2c@fd880000/rtc@6fcpus+cpu-mapcluster0core0 core1 core2 core3 cluster1core0 core1 cluster2core0 core1 cpu@0cpuarm,cortex-a55psci,? F V0,k {@@  cpu@100cpuarm,cortex-a55psci,? k {@@ cpu@200cpuarm,cortex-a55psci,? k {@@ cpu@300cpuarm,cortex-a55psci,? k {@@ cpu@400cpuarm,cortex-a76psci,? F V0,k {@@ cpu@500cpuarm,cortex-a76psci,? k {@@ cpu@600cpuarm,cortex-a76psci,? F V0,k {@@ cpu@700cpuarm,cortex-a76psci,? k {@@  idle-states pscicpu-sleeparm,idle-state->Udfxv l2-cache-l0cache}@ l2-cache-l1cache}@l2-cache-l2cache}@l2-cache-l3cache}@l2-cache-b0cache}@l2-cache-b1cache}@l2-cache-b2cache}@l2-cache-b3cache}@l3-cachecache}0@display-subsystemrockchip,display-subsystemfirmwareopteelinaro,optee-tz%smcscmi arm,scmi-smc+protocol@14 protocol@16pmu-a55arm,cortex-a55-pmupmu-a76arm,cortex-a76-pmupsci arm,psci-1.0%smcclock-0 fixed-clock)׫splltimerarm,armv8-timerP    %sec-physphysvirthyp-physhyp-virtclock-1 fixed-clockn6xin24mclock-2 fixed-clockxin32ksram@10f000 mmio-sram+sram@0arm,scmi-shmemgpu@fb000000*rockchip,rk3588-maliarm,mali-valhall-csf F V ?corecoregroupstacks 0\]^ jobmmugpu#7 EokayLopp-tableoperating-points-v2opp-300000000X _ L L Popp-400000000Xׄ _ L L Popp-500000000Xe _ L L Popp-600000000X#F _ L L Popp-700000000X)' _ ` ` Popp-800000000X/ _ q q Popp-900000000X5 _ 5 5 Popp-1000000000X; _ P P Pusb@fc000000rockchip,rk3588-dwc3snps,dwc3@?ref_clksuspend_clkbus_clkmotg u !zusb2-phyusb3-phy utmi_wide7R Edisabledusb@fc800000"rockchip,rk3588-ehcigeneric-ehci?"u#zusb7Eokayusb@fc840000"rockchip,rk3588-ohcigeneric-ohci?"u#zusb7Eokayusb@fc880000"rockchip,rk3588-ehcigeneric-ehci?$u%zusb7Eokayusb@fc8c0000"rockchip,rk3588-ohcigeneric-ohci?$u%zusb7Eokayusb@fcd00000rockchip,rk3588-dwc3snps,dwc3@(?jihkr&ref_clksuspend_clkbus_clkutmipipemhostu& zusb3-phy utmi_wide4@ Edisablediommu@fc900000 arm,smmu-v3 @qsvoeventqgerrorpriqcmdq-syncZ Edisablediommu@fcb00000 arm,smmu-v3 @}{eventqgerrorpriqcmdq-syncZ Edisabledsyscon@fd58a000)rockchip,rk3588-pmugrfsysconsimple-mfdXfsyscon@fd58c000rockchip,rk3588-sys-grfsysconXasyscon@fd5a4000rockchip,rk3588-vop-grfsysconZ@ bsyscon@fd5a6000rockchip,rk3588-vo-grfsysconZ` ?syscon@fd5a8000rockchip,rk3588-vo-grfsysconZ?csyscon@fd5ac000rockchip,rk3588-usb-grfsysconZ@syscon@fd5b0000rockchip,rk3588-php-grfsyscon[(syscon@fd5bc000$rockchip,rk3588-pipe-phy-grfsyscon[syscon@fd5c4000$rockchip,rk3588-pipe-phy-grfsyscon\@syscon@fd5c8000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d0000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@0rockchip,rk3588-usb2phy?phyclk usb480m_phy0mgphyapb Edisabledotg-ports Edisabled syscon@fd5d8000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@8000rockchip,rk3588-usb2phy?phyclk usb480m_phy2ogphyapbEokay"host-portsEokay~'#syscon@fd5dc000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@+usb2phy@c000rockchip,rk3588-usb2phy?phyclk usb480m_phy3p gphyapbEokay$host-portsEokay%syscon@fd5e0000$rockchip,rk3588-hdptxphy-grfsyscon^syscon@fd5f0000rockchip,rk3588-iocsyscon_sram@fd600000 mmio-sram``+clock-controller@fd7c0000rockchip,rk3588-cru|F]q@VA.2Fq)׫ׄe/ׄ eZ р (i2c@fd880000(rockchip,rk3588-i2crockchip,rk3399-i2c=?ts i2cpclk)default+Eokayfan@18 ti,amc6821regulator@42rockchip,rk8602B vdd_npu_s0dp~0E*regulator-state-memPregulator@43 rockchip,rk8603rockchip,rk8602Cvdd_cpu_big1_s0dp0E*regulator-state-memPrtc@6f isil,isl1208oserial@fd890000&rockchip,rk3588-uartsnps,dw-apb-uartK?baudclkapb_pclki++ntxrx,defaultxEokaypwm@fd8b0000(rockchip,rk3588-pwmrockchip,rk3328-pwm? pwmpclk-default Edisabledpwm@fd8b0010(rockchip,rk3588-pwmrockchip,rk3328-pwm? pwmpclk.default Edisabledpwm@fd8b0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ? pwmpclk/default Edisabledpwm@fd8b0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0? pwmpclk0default Edisabledpower-management@fd8d8000&rockchip,rk3588-pmusysconsimple-mfddpower-controller!rockchip,rk3588-power-controller+Eokaypower-domain@8+power-domain@9  ?!#" 123+power-domain@10 ?!#"4power-domain@11 ?!#"5power-domain@12 ?6789power-domain@13 +power-domain@14(?:power-domain@15 ?;power-domain@16? <=>+power-domain@17 ? ?@Apower-domain@21? BCDEFGHI+power-domain@23?CAJpower-domain@14 ?:power-domain@15?;power-domain@22?Kpower-domain@24?[Z]LM+power-domain@258?ZNpower-domain@268?QOPpower-domain@270?QRST+power-domain@28 ?UVpower-domain@29(?WXpower-domain@30?z{Ypower-domain@31@?WZ[\]power-domain@33!?WZ[power-domain@34"?WZ[power-domain@37%?2^power-domain@38&?45power-domain@40(_video-codec@fdc70000rockchip,rk3588-av1-vpulvdpuFACVׄׄ?AC aclkhclk7 vop@fdd90000rockchip,rk3588-vop BPvopgamma-lut8?]\abcd[7aclkhclkdclk_vp0dclk_vp1dclk_vp2dclk_vp3pclk_vop`7abcd Edisabledports+port@0+port@1+port@2+port@3+iommu@fdd97e00,rockchip,rk3588-iommurockchip,rk3568-iommu ~?]\ aclkifaceZ7 Edisabled`i2s@fddc0000rockchip,rk3588-i2s-tdm?mclk_txmclk_rxhclkFientx7gtx-m  Edisabledi2s@fddf0000rockchip,rk3588-i2s-tdm?445mclk_txmclk_rxhclkF1ientx7gtx-m  Edisabledi2s@fddfc000rockchip,rk3588-i2s-tdm?00,mclk_txmclk_rxhclkF-ienrx7grx-m  Edisabledqos@fdf35000rockchip,rk3588-qossysconP 6qos@fdf35200rockchip,rk3588-qossysconR 7qos@fdf35400rockchip,rk3588-qossysconT 8qos@fdf35600rockchip,rk3588-qossysconV 9qos@fdf36000rockchip,rk3588-qossyscon` Yqos@fdf39000rockchip,rk3588-qossyscon ^qos@fdf3d800rockchip,rk3588-qossyscon _qos@fdf3e000rockchip,rk3588-qossyscon [qos@fdf3e200rockchip,rk3588-qossyscon Zqos@fdf3e400rockchip,rk3588-qossyscon \qos@fdf3e600rockchip,rk3588-qossyscon ]qos@fdf40000rockchip,rk3588-qossyscon Wqos@fdf40200rockchip,rk3588-qossyscon Xqos@fdf40400rockchip,rk3588-qossyscon Qqos@fdf40500rockchip,rk3588-qossyscon Rqos@fdf40600rockchip,rk3588-qossyscon Sqos@fdf40800rockchip,rk3588-qossyscon Tqos@fdf41000rockchip,rk3588-qossyscon Uqos@fdf41100rockchip,rk3588-qossyscon Vqos@fdf60000rockchip,rk3588-qossyscon <qos@fdf60200rockchip,rk3588-qossyscon =qos@fdf60400rockchip,rk3588-qossyscon >qos@fdf61000rockchip,rk3588-qossyscon ?qos@fdf61200rockchip,rk3588-qossyscon @qos@fdf61400rockchip,rk3588-qossyscon Aqos@fdf62000rockchip,rk3588-qossyscon :qos@fdf63000rockchip,rk3588-qossyscon0 ;qos@fdf64000rockchip,rk3588-qossyscon@ Jqos@fdf66000rockchip,rk3588-qossyscon` Bqos@fdf66200rockchip,rk3588-qossysconb Cqos@fdf66400rockchip,rk3588-qossyscond Dqos@fdf66600rockchip,rk3588-qossysconf Eqos@fdf66800rockchip,rk3588-qossysconh Fqos@fdf66a00rockchip,rk3588-qossysconj Gqos@fdf66c00rockchip,rk3588-qossysconl Hqos@fdf66e00rockchip,rk3588-qossysconn Iqos@fdf67000rockchip,rk3588-qossysconp Kqos@fdf67200rockchip,rk3588-qossysconr qos@fdf70000rockchip,rk3588-qossyscon 4qos@fdf71000rockchip,rk3588-qossyscon 5qos@fdf72000rockchip,rk3588-qossyscon 1qos@fdf72200rockchip,rk3588-qossyscon" 2qos@fdf72400rockchip,rk3588-qossyscon$ 3qos@fdf80000rockchip,rk3588-qossyscon Nqos@fdf81000rockchip,rk3588-qossyscon Oqos@fdf81200rockchip,rk3588-qossyscon Pqos@fdf82000rockchip,rk3588-qossyscon Lqos@fdf82200rockchip,rk3588-qossyscon" Mdfi@fe060000rockchip,rk3588-dfi@&0:fpcie@fe180000*rockchip,rk3588-pcierockchip,rk3568-pcie0?0?CH>MR)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr'8`KggggYjy0h0u& zpcie-phy7"T @ @0 @@dbiapbconfig). gpwrpipe+ Edisabledlegacy-interrupt-controller' gpcie@fe190000*rockchip,rk3588-pcierockchip,rk3568-pcie@O0?DI?NSs)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr'8`KiiiiYjy@h@uj zpcie-phy7"T @ @0 A@dbiapbconfig*/ gpwrpipe+ Edisabledlegacy-interrupt-controller' iethernet@fe1c0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(?67Y^50stmmacethclk_mac_refpclk_macaclk_macptp_ref7!$ gstmmacetha(klm Edisabledmdiosnps,dwmac-mdio+stmmac-axi-config krx-queues-config+lqueue0queue1tx-queues-configAmqueue0queue1sata@fe210000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci!(?b_eTosatapmaliverxoobrefasicW+ Edisabledsata-port@0i@uj zsata-phyv  sata@fe230000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci#(?dagVqsatapmaliverxoobrefasicW+ Edisabledsata-port@0i@u& zsata-phyv  spi@fe2b0000 rockchip,sfc+@?/0clk_sfchclk_sfc+ Edisabledmmc@fe2c00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc,@ ?  biuciuciu-driveciu-sampleрdefault nop7(Eokayq+rmmc@fe2d00000rockchip,rk3588-dw-mshcrockchip,rk3288-dw-mshc-@ ?biuciuciu-driveciu-sample defaults7% Edisabledmmc@fe2e0000rockchip,rk3588-dwcmshc.F-., V n6 (?,*+-.corebusaxiblocktimer tuvwdefault(gcorebusaxiblocktimerEokay8JWfuxq+yi2s@fe470000rockchip,rk3588-i2s-tdmG?+/(mclk_txmclk_rxhclkF)-i++ntxrx7&*+ gtx-mrx-mdefault(z{|}~  Edisabledi2s@fe480000rockchip,rk3588-i2s-tdmH?y}umclk_txmclk_rxhclki++ntxrx^_ gtx-mrx-mdefault(  Edisabledi2s@fe490000(rockchip,rk3588-i2srockchip,rk3066-i2sI?i2s_clki2s_hclkFintxrx7&default  Edisabledi2s@fe4a0000(rockchip,rk3588-i2srockchip,rk3066-i2sJ?%i2s_clki2s_hclkF"intxrx7&default  Edisabledinterrupt-controller@fe600000 arm,gic-v3 `h a8'+msi-controller@fe640000arm,gic-v3-itsd hmsi-controller@fe660000arm,gic-v3-itsf ppi-partitionsinterrupt-partition-0 interrupt-partition-1  dma-controller@fea10000arm,pl330arm,primecell@ VW ?n apb_pclk -+dma-controller@fea30000arm,pl330arm,primecell@ XY ?o apb_pclk -i2c@fea90000(rockchip,rk3588-i2crockchip,rk3399-i2c?{ i2cpclk>default+ Edisabledi2c@feaa0000(rockchip,rk3588-i2crockchip,rk3399-i2c?| i2cpclk?default+ Edisabledi2c@feab0000(rockchip,rk3588-i2crockchip,rk3399-i2c?} i2cpclk@default+ Edisabledi2c@feac0000(rockchip,rk3588-i2crockchip,rk3399-i2c?~ i2cpclkAdefault+ Edisabledi2c@fead0000(rockchip,rk3588-i2crockchip,rk3399-i2c? i2cpclkBdefault+ Edisabledtimer@feae0000,rockchip,rk3588-timerrockchip,rk3288-timer !?TW pclktimerwatchdog@feaf0000 rockchip,rk3588-wdtsnps,dw-wdt?dc tclkpclk;spi@feb00000(rockchip,rk3588-spirockchip,rk3066-spiF?spiclkapb_pclki++ntxrx 8 default+ Edisabledspi@feb10000(rockchip,rk3588-spirockchip,rk3066-spiG?spiclkapb_pclki++ntxrx 8 default+ Edisabledspi@feb20000(rockchip,rk3588-spirockchip,rk3066-spiH?spiclkapb_pclkintxrx 8default+EokayFV pmic@0rockchip,rk806  ? Odefault [B@ m * * * * * * * * * *  *  % 2*dvs1-null-pins >gpio_pwrctrl1 Cpin_fun0dvs2-null-pins >gpio_pwrctrl2 Cpin_fun0dvs3-null-pins >gpio_pwrctrl3 Cpin_fun0regulatorsdcdc-reg1dp~00 vdd_gpu_s0 Lregulator-state-memPdcdc-reg2vdd_cpu_lit_s0dp~00 regulator-state-memPdcdc-reg3 vdd_log_s0 L q00regulator-state-memP h qdcdc-reg4 vdd_vdenc_s0dp~00regulator-state-memPdcdc-reg5 vdd_ddr_s0 L 00regulator-state-memP h Pdcdc-reg6 vdd2_ddr_s3regulator-state-mem dcdc-reg7vdd_2v0_pldo_s300regulator-state-mem  hdcdc-reg8 vcc_3v3_s32Z2Zqregulator-state-mem  h2Zdcdc-reg9 vddq_ddr_s0regulator-state-memPdcdc-reg10 vcc_1v8_s3w@w@yregulator-state-mem  hw@pldo-reg1 vcca_1v8_s0w@w@regulator-state-memPpldo-reg2 vcc_1v8_s0w@w@regulator-state-memP hw@pldo-reg3 vdda_1v2_s0OOregulator-state-memPpldo-reg4 vcca_3v3_s02Z2Z00regulator-state-memPpldo-reg5 vccio_sd_s0w@2Z00rregulator-state-memPpldo-reg6 pldo6_s3w@w@regulator-state-mem  hw@nldo-reg1 vdd_0v75_s3 q qregulator-state-mem  h qnldo-reg2vdda_ddr_pll_s0 P Pregulator-state-memP h Pnldo-reg3 vdda_0v75_s0 q qregulator-state-memPnldo-reg4 vdda_0v85_s0 P Pregulator-state-memPnldo-reg5 vdd_0v75_s0 q qregulator-state-memPspi@feb30000(rockchip,rk3588-spirockchip,rk3066-spiI?spiclkapb_pclkintxrx 8 default+ Edisabledserial@feb40000&rockchip,rk3588-uartsnps,dw-apb-uartL?baudclkapb_pclki++ ntxrxdefaultx Edisabledserial@feb50000&rockchip,rk3588-uartsnps,dw-apb-uartM?baudclkapb_pclki+ + ntxrxdefaultxEokayserial@feb60000&rockchip,rk3588-uartsnps,dw-apb-uartN?baudclkapb_pclki+ + ntxrxdefaultxEokay serial@feb70000&rockchip,rk3588-uartsnps,dw-apb-uartO?baudclkapb_pclki ntxrxdefaultx Edisabledserial@feb80000&rockchip,rk3588-uartsnps,dw-apb-uartP?baudclkapb_pclki ntxrxdefaultx Edisabledserial@feb90000&rockchip,rk3588-uartsnps,dw-apb-uartQ?baudclkapb_pclki ntxrxdefaultx Edisabledserial@feba0000&rockchip,rk3588-uartsnps,dw-apb-uartR?baudclkapb_pclkieentxrxdefaultxEokayserial@febb0000&rockchip,rk3588-uartsnps,dw-apb-uartS?baudclkapb_pclkie e ntxrxdefaultx Edisabledserial@febc0000&rockchip,rk3588-uartsnps,dw-apb-uartT?baudclkapb_pclkie e ntxrxdefaultx Edisabledpwm@febd0000(rockchip,rk3588-pwmrockchip,rk3328-pwm?LK pwmpclkdefault Edisabledpwm@febd0010(rockchip,rk3588-pwmrockchip,rk3328-pwm?LK pwmpclkdefault Edisabledpwm@febd0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ?LK pwmpclkdefault Edisabledpwm@febd0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0?LK pwmpclkdefault Edisabledpwm@febe0000(rockchip,rk3588-pwmrockchip,rk3328-pwm?ON pwmpclkdefault Edisabledpwm@febe0010(rockchip,rk3588-pwmrockchip,rk3328-pwm?ON pwmpclkdefault Edisabledpwm@febe0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ?ON pwmpclkdefault Edisabledpwm@febe0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0?ON pwmpclkdefault Edisabledpwm@febf0000(rockchip,rk3588-pwmrockchip,rk3328-pwm?RQ pwmpclkdefault Edisabledpwm@febf0010(rockchip,rk3588-pwmrockchip,rk3328-pwm?RQ pwmpclkdefault Edisabledpwm@febf0020(rockchip,rk3588-pwmrockchip,rk3328-pwm ?RQ pwmpclkdefault Edisabledpwm@febf0030(rockchip,rk3588-pwmrockchip,rk3328-pwm0?RQ pwmpclkdefault Edisabledtsadc@fec00000rockchip,rk3588-tsadc?tsadcapb_pclkFVVWgtsadc-apbtsadc     gpiootpout Eokayadc@fec10000rockchip,rk3588-saradc &?saradcapb_pclkU gsaradc-apbEokay 8i2c@fec80000(rockchip,rk3588-i2crockchip,rk3399-i2c? i2cpclkCdefault+ Edisabledi2c@fec90000(rockchip,rk3588-i2crockchip,rk3399-i2c? i2cpclkDdefault+Eokayeeprom@54st,24c04atmel,24c04T D Mqi2c@feca0000(rockchip,rk3588-i2crockchip,rk3399-i2c? i2cpclkEdefault+Eokayregulator@42rockchip,rk8602Bvdd_cpu_big0_s0dp0E*regulator-state-memPspi@fecb0000(rockchip,rk3588-spirockchip,rk3066-spiJ?spiclkapb_pclkie entxrx 8 default+ Edisabledefuse@fecc0000rockchip,rk3588-otp ?otpapb_pclkphyarb gotpapbarb+cpu-code@2id@7cpu-leakage@17cpu-leakage@18cpu-leakage@19log-leakage@1agpu-leakage@1bcpu-version@1c Xnpu-leakage@28(codec-leakage@29)dma-controller@fed10000arm,pl330arm,primecell@ Z[ ?p apb_pclk -ephy@fed60000rockchip,rk3588-hdptx-phy ?Trefapbs8#cde!""gphyapbinitcmnlaneroplllcpll Edisabledphy@fed80000rockchip,rk3588-usbdp-phys?lVrefclkimmortalpclkutmi(   ginitcmnlanepcs_apbpma_apb ] p   Edisabled!phy@fee00000rockchip,rk3588-naneng-combphy?vW refapbpipeFVs<Cgphyapb (  Edisabledjphy@fee20000rockchip,rk3588-naneng-combphy?xW refapbpipeFVs>Egphyapb (  Edisabled&sram@ff001000 mmio-sram+pinctrlrockchip,rk3588-pinctrl+gpio@fd8a0000rockchip,gpio-bank?qr ?  O'gpio@fec20000rockchip,gpio-bank?st ?  O'mdot2e-w-disable1-n-hog   m.2 E-key W_DISABLE1# gpio@fec30000rockchip,gpio-bank?uv ? @  O'gpio@fec40000rockchip,gpio-bank?wx ? `  O'gpio@fec50000rockchip,gpio-bank?yz ?  O'mdot2e-w-disable2-n-hog   m.2 E-key W_DISABLE2# pcfg-pull-up pcfg-pull-down pcfg-pull-none pcfg-pull-none-drv-level-2  (pcfg-pull-up-drv-level-1  (pcfg-pull-up-drv-level-2  (pcfg-pull-none-smt  7auddsmbt1120can0can1can2cifclk32kcpuddrphych0ddrphych1ddrphych2ddrphych3dp0dp1emmcemmc-bus8 Ltemmc-clk Lvemmc-cmd Luemmc-data-strobe Lwemmc-reset Leth1fspigmac1gpuhdmii2c0i2c0m2-xfer L)i2c1i2c1m4-xfer L  i2c2i2c2m0-xfer L  i2c3i2c3m0-xfer L  i2c4i2c4m0-xfer L  i2c5i2c5m0-xfer L  i2c6i2c6m4-xfer L  i2c7i2c7m0-xfer L  i2c8i2c8m2-xfer L  i2s0i2s0-lrck Lzi2s0-sclk L{i2s0-sdi0 L|i2s0-sdi1 L}i2s0-sdi2 L~i2s0-sdi3 Li2s0-sdo0 Li2s0-sdo1 Li2s0-sdo2 Li2s0-sdo3 Li2s1i2s1m0-lrck Li2s1m0-sclk Li2s1m0-sdi0 Li2s1m0-sdi1 Li2s1m0-sdi2 Li2s1m0-sdi3 Li2s1m0-sdo0 L i2s1m0-sdo1 L i2s1m0-sdo2 L i2s1m0-sdo3 L i2s2i2s2m1-lrck Li2s2m1-sclk L i2s2m1-sdi L i2s2m1-sdo L i2s3i2s3-lrck Li2s3-sclk Li2s3-sdi Li2s3-sdo Ljtaglitcpumcumipinpupcie20x1pcie30phypcie30x1pcie30x2pcie30x4pcie30x4-clkreqn-m0 Lpcie30x4-perstn-m0 Lpcie30x4-waken-m0 L pdm0pdm1pmicpmic-pinsp Lpmupwm0pwm0m0-pins L-pwm1pwm1m0-pins L.pwm2pwm2m0-pins L/pwm3pwm3m0-pins L0pwm4pwm4m0-pins L pwm5pwm5m0-pins L pwm6pwm6m0-pins L pwm7pwm7m0-pins L pwm8pwm8m0-pins L pwm9pwm9m0-pins L pwm10pwm10m0-pins L pwm11pwm11m0-pins L pwm12pwm12m0-pins L pwm13pwm13m0-pins L pwm14pwm14m0-pins L pwm15pwm15m0-pins L refclksatasata0sata1sata2sdiosdiom1-pins` Lssdmmcsdmmc-bus4@ Lnsdmmc-clk Lpsdmmc-cmd Lospdif0spdif1spi0spi0m0-pins0 Lspi0m0-cs0 Lspi0m0-cs1 Lspi1spi1m1-pins0 Lspi1m1-cs0 Lspi1m1-cs1 Lspi2spi2m2-pins0 L spi2m2-cs0 L spi3spi3m1-pins0 L spi3m1-cs0 Lspi3m1-cs1 Lspi4spi4m0-pins0 Lspi4m0-cs0 Lspi4m0-cs1 Ltsadctsadc-shut Luart0uart0m0-xfer L,uart1uart1m1-xfer L  uart2uart2m0-xfer L uart3uart3m2-xfer L  uart3-rtsn L uart4uart4m1-xfer L  uart5uart5m1-xfer L  uart6uart6m1-xfer L  uart7uart7m0-xfer L  uart8uart8m1-xfer L  uart9uart9m1-xfer L  vopbt656gpio-functsadc-gpio-func Leth0eth0-pins Lgmac0gmac0-miim Lgmac0-rx-bus20 Lgmac0-tx-bus20 Lgmac0-rgmii-clk L gmac0-rgmii-bus@ L  etherneteth-reset Lledsled1-pin Lusb@fc400000rockchip,rk3588-dwc3snps,dwc3@@?ref_clksuspend_clkbus_clkmotg uzusb2-phyusb3-phy utmi_wide7S Edisabledsyscon@fd5b8000%rockchip,rk3588-pcie3-phy-grfsyscon[syscon@fd5c0000$rockchip,rk3588-pipe-phy-grfsyscon\syscon@fd5cc000$rockchip,rk3588-usbdpphy-grfsyscon\@syscon@fd5d4000.rockchip,rk3588-usb2phy-grfsysconsimple-mfd]@@+usb2phy@4000rockchip,rk3588-usb2phy@?phyclk usb480m_phy1ngphyapb Edisabledotg-ports Edisabledi2s@fddc8000rockchip,rk3588-i2s-tdm܀?mclk_txmclk_rxhclkFientx7gtx-m  Edisabledi2s@fddf4000rockchip,rk3588-i2s-tdm@?99?mclk_txmclk_rxhclkF6ientx7gtx-m  Edisabledi2s@fddf8000rockchip,rk3588-i2s-tdm߀?++'mclk_txmclk_rxhclkF(ienrx7grx-m  Edisabledi2s@fde00000rockchip,rk3588-i2s-tdm?&&"mclk_txmclk_rxhclkF#ienrx7grx-m  Edisabledpcie@fe150000*rockchip,rk3588-pcierockchip,rk3568-pcie+4?@E;JOt-aclk_mstaclk_slvaclk_dbipclkauxpiperefpciPsyspmcmsglegacyerr'8`KYjyu zpcie-phy7"T @ @0 @@dbiapbconfig&+ gpwrpipeEokaydefault Z flegacy-interrupt-controller' pcie@fe160000*rockchip,rk3588-pcierockchip,rk3568-pcie+0?AF<KPu)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr'8`KYjyu zpcie-phy7"T @ @@0 @@@dbiapbconfig', gpwrpipe Edisabledlegacy-interrupt-controller' pcie@fe170000*rockchip,rk3588-pcierockchip,rk3568-pcie /0?BG=LQ)aclk_mstaclk_slvaclk_dbipclkauxpipepciPsyspmcmsglegacyerr'8`KYjy h u zpcie-phy7"T @ @0 @@dbiapbconfig(- gpwrpipe+Eokay Z  flegacy-interrupt-controller' ethernet@fe1b0000&rockchip,rk3588-gmacsnps,dwmac-4.20a macirqeth_wake_irq(?67X]40stmmacethclk_mac_refpclk_macaclk_macptp_ref7!# gstmmacetha(Eokay voutput  rgmii~default     'mdiosnps,dwmac-mdio+ethernet-phy@6ethernet-phy-ieee802.3-c22?stmmac-axi-config rx-queues-config+queue0queue1tx-queues-configAqueue0queue1sata@fe220000'rockchip,rk3588-dwc-ahcisnps,dwc-ahci"(?c`fUpsatapmaliverxoobrefasicW+ Edisabledsata-port@0i@u zsata-phyv  phy@fed90000rockchip,rk3588-usbdp-phys?mWrefclkimmortalpclkutmi(ginitcmnlanepcs_apbpma_apb ] p   Edisabledphy@fee10000rockchip,rk3588-naneng-combphy?wW refapbpipeFVs=Dgphyapb ( Eokayphy@fee80000rockchip,rk3588-pcie3-phys?ypclkHgphy ( Eokayadc-keys adc-keys  buttons w@ ,dbutton-bios-disable :BIOS_DISABLE @h Kchosen eserial2:115200n8dc-12v-regulatorregulator-fixeddc_12vemmc-pwrseqmmc-pwrseq-emmcdefault Zxleds gpio-ledsdefaultled-1  Cheartbeat qheartbeat pcie-refclk-gen-clock fixed-clockpcie-refclk-clockgpio-gate-clock? defaultpps pps-gpio vcc-1v1-nldo-s3-regulatorregulator-fixedvcc_1v1_nldo_s3E*vcc-1v2-s3-regulatorregulator-fixed vcc_1v2_s3OOE*vcc-2v8-s3-regulatorregulator-fixed vcc_2v8_s3**Eqvcc-5v0-usb-a-regulatorregulator-fixed usb_a_vccLK@LK@E*   'vcc-5v0-usb-c1-regulatorregulator-fixed 5v_usbc1LK@LK@E  vcc-5v0-usb-c2-regulatorregulator-fixed 5v_usbc2LK@LK@E  vcc3v3-mdot2-regulatorregulator-fixed vcc3v3_mdot22Z2ZEvcc5v0-sys-regulatorregulator-fixed vcc5v0_sysLK@LK@E*vcc5v0-usb-regulatorregulator-fixed vcc5v0_usbLK@LK@E* compatibleinterrupt-parent#address-cells#size-cellsmodelgpio0gpio1gpio2gpio3gpio4i2c0i2c1i2c2i2c3i2c4i2c5i2c6i2c7i2c8serial0serial1serial2serial3serial4serial5serial6serial7serial8serial9spi0spi1spi2spi3spi4ethernet0mmc0mmc1rtc0cpudevice_typeregenable-methodcapacity-dmips-mhzclocksassigned-clocksassigned-clock-ratescpu-idle-statesi-cache-sizei-cache-line-sizei-cache-setsd-cache-sized-cache-line-sized-cache-setsnext-level-cachedynamic-power-coefficient#cooling-cellscpu-supplyphandleentry-methodlocal-timer-stoparm,psci-suspend-paramentry-latency-usexit-latency-usmin-residency-uscache-levelcache-unifiedportsarm,smc-idshmem#clock-cells#reset-cellsinterruptsclock-frequencyclock-output-namesinterrupt-namesrangesclock-namesoperating-points-v2power-domainsstatusmali-supplyopp-hzopp-microvoltdr_modephysphy-namesphy_typeresetssnps,dis_enblslpm_quirksnps,dis-u1-entry-quirksnps,dis-u2-entry-quirksnps,dis-u2-freeclk-exists-quirksnps,dis-del-phy-power-chg-quirksnps,dis-tx-ipgap-linecheck-quirksnps,dis_rxdet_inp3_quirk#iommu-cellsreset-names#phy-cellsphy-supplyrockchip,grfpinctrl-0pinctrl-namesfcs,suspend-voltage-selectorregulator-nameregulator-always-onregulator-boot-onregulator-min-microvoltregulator-max-microvoltregulator-ramp-delayvin-supplyregulator-off-in-suspenddmasdma-namesreg-shiftreg-io-width#pwm-cells#power-domain-cellspm_qosreg-namesiommusrockchip,vop-grfrockchip,vo1-grfrockchip,pmuassigned-clock-parents#sound-dai-cellsbus-range#interrupt-cellsinterrupt-map-maskinterrupt-maplinux,pci-domainmax-link-speedmsi-mapnum-lanesinterrupt-controllerrockchip,php-grfsnps,axi-configsnps,mixed-burstsnps,mtl-rx-configsnps,mtl-tx-configsnps,tsosnps,blensnps,wr_osr_lmtsnps,rd_osr_lmtsnps,rx-queues-to-usesnps,tx-queues-to-useports-implementedhba-port-capsnps,rx-ts-maxsnps,tx-ts-maxfifo-depthmax-frequencybroken-cdbus-widthcap-sd-highspeeddisable-wpsd-uhs-sdr12sd-uhs-sdr25sd-uhs-sdr50sd-uhs-ddr50sd-uhs-sdr104vmmc-supplyvqmmc-supplycap-mmc-highspeedmmc-ddr-1_8vmmc-hs200-1_8vmmc-hs400-1_8vmmc-hs400-enhanced-strobemmc-pwrseqno-sdiono-sdnon-removablesupports-cqerockchip,trcm-sync-tx-onlymbi-aliasmbi-rangesmsi-controller#msi-cellsaffinityarm,pl330-periph-burst#dma-cellsnum-csgpio-controller#gpio-cellsspi-max-frequencysystem-power-controllervcc1-supplyvcc2-supplyvcc3-supplyvcc4-supplyvcc5-supplyvcc6-supplyvcc7-supplyvcc8-supplyvcc9-supplyvcc10-supplyvcc11-supplyvcc12-supplyvcc13-supplyvcc14-supplyvcca-supplypinsfunctionregulator-enable-ramp-delayregulator-suspend-microvoltregulator-on-in-suspendlinux,rs485-enabled-at-boot-timerockchip,hw-tshut-temprockchip,hw-tshut-moderockchip,hw-tshut-polaritypinctrl-1#thermal-sensor-cells#io-channel-cellsvref-supplypagesizevcc-supplybitsrockchip,u2phy-grfrockchip,usb-grfrockchip,usbdpphy-grfrockchip,vo-grfrockchip,pipe-grfrockchip,pipe-phy-grfgpio-rangesgpiosoutput-lowline-namegpio-hogbias-pull-upbias-pull-downbias-disabledrive-strengthinput-schmitt-enablerockchip,pinsreset-gpiosvpcie3v3-supplyclock_in_outphy-handlephy-modetx_delayrx_delaysnps,reset-gpiosnps,reset-active-lowsnps,reset-delays-usrockchip,phy-grfio-channelsio-channel-nameskeyup-threshold-microvoltpoll-intervallabellinux,codepress-threshold-microvoltstdout-pathlinux,default-triggercolorenable-gpiosenable-active-high